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OLD_SHURIK
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Registered: ‎12-23-2020

vivado - zynq7000 - ethernet - emio - GMII

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Hello.
Vivado 2018.2
Ethernet 10/100/1000 - ETH0 over EMIO.
Ethernet PHY operates on the GMII protocol.
Why is the signal "GMII_ETHERNET_0_0_tx_clk: in STD_LOGIC;" is the INPUT?
It should be an OUTPUT like all other signals for TX.
How can this be fixed ?!


GMII_ETHERNET_0_0_col : in STD_LOGIC;
GMII_ETHERNET_0_0_crs : in STD_LOGIC;
GMII_ETHERNET_0_0_rx_clk : in STD_LOGIC;
GMII_ETHERNET_0_0_rx_dv : in STD_LOGIC;
GMII_ETHERNET_0_0_rx_er : in STD_LOGIC;
GMII_ETHERNET_0_0_rxd : in STD_LOGIC_VECTOR ( 7 downto 0 );
GMII_ETHERNET_0_0_tx_clk : in STD_LOGIC;                                                           -- ??? INPUT ????
GMII_ETHERNET_0_0_tx_en : out STD_LOGIC_VECTOR ( 0 to 0 );
GMII_ETHERNET_0_0_tx_er : out STD_LOGIC_VECTOR ( 0 to 0 );
GMII_ETHERNET_0_0_txd : out STD_LOGIC_VECTOR ( 7 downto 0 );



Sincerely, Alexander.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@OLD_SHURIK You can reference the Zynq-7000 SoC Technical Reference Manual (UG585; v1.12.2) in Chapter 16: Gigabit Ethernet Controller in Figure 16-8: GMII Interface via EMIO Connections and Table 16-12: Ethernet GMII/MII Interface Signals via EMIO Interface.

forums_z7000_gmii_emio.png

 

forums_z7000_gmii_emio_table.png

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miker
Xilinx Employee
Xilinx Employee
443 Views
Registered: ‎11-30-2007

@OLD_SHURIK You can reference the Zynq-7000 SoC Technical Reference Manual (UG585; v1.12.2) in Chapter 16: Gigabit Ethernet Controller in Figure 16-8: GMII Interface via EMIO Connections and Table 16-12: Ethernet GMII/MII Interface Signals via EMIO Interface.

forums_z7000_gmii_emio.png

 

forums_z7000_gmii_emio_table.png

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zhus116
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Registered: ‎02-27-2019

您好,请问GMII模式下,用PL的EMIO来扩展一个千兆网口,其中GTX_CLK的时钟该怎么由Zynq7035的MAC产生125M给PHY芯片。(PHY芯片用的是88E1111-BAB11000芯片。)

方案一:可以由Zynq7035的PL的IP core用一个锁相环产生125M给PHY芯片吗,

方案二:或者由PHY芯片产生的125M时钟输出先给PL,然后PL内部回环给GTX_CLK,这样可以吗?

谢谢您了,希望能得到您的回复!

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