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Adventurer
Adventurer
8,456 Views
Registered: ‎12-06-2010

whta is clock speed in SRIO Interface on Virtex-7 FPGA

Hi,

 

I am using Virtex-7 FPGA (xc7vx415tffg1157) and i want to conenct Two x1 GTH transceiver port from FPGA to  to SRIO switch. My SRIO speed should support upto 5Gbps. So, i need to connect  reference clock for SRIO interface. Can you please tell me the clock input range for FPGA GTH port.

 

 

Magalingam

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6 Replies
Xilinx Employee
Xilinx Employee
8,450 Views
Registered: ‎02-06-2013

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

Hi

 

If you are using the SRIO core then reference clock of 125Mhz is needed to operate upto 5Gbps.

 

If using the wizard to support only the phy layer it supports various reference clocks which you can check using the

transceiver wizard.

 

Refer PG007 clocking section if using the core.

Regards,

Satish

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Adventurer
Adventurer
8,444 Views
Registered: ‎12-06-2010

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

athish,

 

Thank you.

 

 

 

Magalingam

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Adventurer
Adventurer
8,441 Views
Registered: ‎12-06-2010

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

sathish,

 

Thank you.

 

 

 

Magalingam

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Adventurer
Adventurer
8,439 Views
Registered: ‎12-06-2010

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

Can you provide reference scheamatics for Virtex-7 FPGA with SRIO interface?

 

 

Magalingam

 

 

 

 

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Xilinx Employee
Xilinx Employee
8,421 Views
Registered: ‎08-01-2012

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

Also the following AR http://www.xilinx.com/support/answers/58402.html may give some more useful information for your requirement

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Xilinx Employee
Xilinx Employee
8,389 Views
Registered: ‎02-06-2013

Re: whta is clock speed in SRIO Interface on Virtex-7 FPGA

Hi

 

Kintex7 and Virtex7 boards can be used for SRIO connectivity,Where the GT's can be used to Implement the SRIO functionality.

 

There are no specific Schematics for SRIO,You can check VC707 and VC709 schematics for reference.

 

Have a look at below post  where one of the possible connections is mentioned.

 

http://forums.xilinx.com/t5/7-Series-FPGAs/SRIO-multi-lane-connection-problem/td-p/412189

Regards,

Satish

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