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Voyager
Voyager
246 Views
Registered: ‎10-12-2016

why signal_detect as input to ethernet Xilinx IP ?

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Hi friends,

Xilinx gmii_sgmii_bridge signal_detect input -- Based on my GT understanding, this signal should have been driven from the Rx GT. Most likely CDR block would drive it, distinguishing between Electrical Idle and valid signal toggling. I am not sure why this signal is brought out as input, and how it should be driven.

 

signal_detec_for_ethernet_to_XILINX_posted.PNG

Any help or suggestions are highly appreciated.

-Sampath

 

-Sampath
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Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎05-01-2013

回复: why signal_detect as input to ethernet Xilinx IP ?

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Some external PHY devices provide "signal_detect" signal to indicate if the link is available.

Then you can use it to the Ethernet IP input.

If there's no such signal on you board, you can just connect it to VCC.

 

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Xilinx Employee
Xilinx Employee
197 Views
Registered: ‎05-01-2013

回复: why signal_detect as input to ethernet Xilinx IP ?

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Some external PHY devices provide "signal_detect" signal to indicate if the link is available.

Then you can use it to the Ethernet IP input.

If there's no such signal on you board, you can just connect it to VCC.

 

View solution in original post

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Voyager
Voyager
172 Views
Registered: ‎10-12-2016

回复: why signal_detect as input to ethernet Xilinx IP ?

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Thank you.
-Sampath
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Observer aforencich
Observer
55 Views
Registered: ‎08-14-2013

Re: why signal_detect as input to ethernet Xilinx IP ?

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Many optical transceiver modules have a signal detect output pin that goes active when the optical power at the receiver passes a certain threshold.  I'm not even sure what the core does with that signal aside from perhaps preventing any garbage data from passing through the PHY when there is no light entering the transceiver.  I usually just tie the signal detect pins high; the downstream logic should be smart enough to deal with any garbage from the transceiver before the link is up. 

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