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Observer bwerth
Observer
2,369 Views
Registered: ‎06-17-2016

xapp 1306 top module designation

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Hi Everyone,

I've been trying to implement the xapp 1306 pl 1g ethernet reference design, but when I try to compile the project in IDE, it asks for a top module and complains that there aren't any modules in the design. Has anyone else run into this issue with this reference design or application note? Thanks for any help.
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Explorer
Explorer
4,276 Views
Registered: ‎04-12-2017

Re: xapp 1306 top module designation

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Does it have a block design (IP integrator)?

 

If it does, you have to make and HDL wrapper for the block design.

Avi Chami MSc
FPGA Site
3 Replies
Explorer
Explorer
4,277 Views
Registered: ‎04-12-2017

Re: xapp 1306 top module designation

Jump to solution

Does it have a block design (IP integrator)?

 

If it does, you have to make and HDL wrapper for the block design.

Avi Chami MSc
FPGA Site
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Xilinx Employee
Xilinx Employee
2,308 Views
Registered: ‎02-06-2013

Re: xapp 1306 top module designation

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Hi

 

Are you following the steps mentioned in below link as is to implement the design

 

http://www.wiki.xilinx.com/PS+and+PL+based+Ethernet+in+Zynq+MPSoC

Regards,

Satish

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Observer bwerth
Observer
2,303 Views
Registered: ‎06-17-2016

Re: xapp 1306 top module designation

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Hi,

 

   That ended up working, thank you for the comment.

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