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Visitor
Visitor
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Registered: ‎05-08-2020

xilinx Tri-Mode in **REVERSE** MII (GMII/RGMII/etc). mode

OK, I do schematics and PCBs, not really VHDL per se. Thus Xilinx LogiCOREs are not really my thing. 

Nevertheless, I would like to do a _direct_ MAC-to-MAC connection between my (Multi-MAC network-)CPU of choice and our Xilinx Artix-7 FPGA. Naturally, this will require the FPGA to enter a **Reverse** (Not [necessarily] Reduced) MII/GMII/whatever mode.

In other words I need the FPGA to take on the role of an PHY. Or more precisely to emulate two back-to-back connected PHYs, positioned in between the Tri-Mode Ethernet MAC IP block and the physical pins of the FPGA. 

 

I need to know whether or not this Artix-7 FPGA can be configured for this. That is, whether there is a ready-made IP block for this (I am not going to ask our VHDL developer to do this, ethernet was hard enough as it was…) 

• https://www.eetimes.com/reverse-media-independent-interface-revmii-block-architecture/

 

Reverse MII, Emulated PHY-to-PHYReverse MII, Emulated PHY-to-PHY

 

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @HW-Designer ,

Please check if PCS/PMA or SGMII IP is suitable for you. (PG047)

You can generate the IP in either MAC mode or PHY mode and connect it back to back.

 

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Scholar
Scholar
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Registered: ‎08-07-2014

@HW-Designer

In other words I need the FPGA to take on the role of an PHY. Or more precisely to emulate two back-to-back connected PHYs, positioned in between the Tri-Mode Ethernet MAC IP block and the physical pins of the FPGA.

You just need to have a pair of FIFOs between the PHY and the MAC core. The lines (Rx) coming from the PHY will enter a rx_fifo. The output from the rx_fifo, one tap will go to the MAC core and the other must to the Tx lines for the 2nd PHY. Then the Tx lines coming from the MAC needs to be MUXed with the Rx lines tap from the rx_fifo before entering the tx_fifo. The o/p of the tx_fifo will be connected to the PHY. You need to somehow control this MUX as the MAC Tx cannot send data out when rx_fifo rx lines are connected to the tx_fifo.

Yes the protocol doesn't matter, all signals go in and go out of the FIFO like a bus other than the clocks.

------------FPGA enthusiast------------
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Visitor
Visitor
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Registered: ‎05-08-2020

Well, yeees. But not really.

This PCS/PMA LogiCORE is apparently a translator from GMII to either SGMII or else directly to the Ethernet Physical Coding Sublayer, for immediate attachment to an external Physical Medium Attachment analog driver/buffer. In other words all the digital parts of an actual PHY. Which is more or less exactly what I want to emulate away. 

 

I suppose I could ask our VHDL developer to connect two instances of this LogiCORE back to back in SGMII mode, in a « GMII<->SGMII<=>SGMII<->GMII » fashion. That might work. However, I feel like this solution is more than a little 'excessive' for what I need. What I need is really not much more than a GMII cross-switch fabric. A fancy MUX, really. With clock support and preferably a minimal MDIO implementation to keep the CPU side of things happy. 

 

For CPUs with a SGMII interface on their own, this LogiCORE would probably fit the bill, though. 

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Visitor
Visitor
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Registered: ‎05-08-2020

« The Tx lines of the FPGA MAC will get data from the Rx lines of the CPU MAC and the Rx lines of the FPGA MAC will feed the Tx lines of the CPU MAC, right? » 

 

Not really. The MII interface is asymmetric. There is a distinct MAC role, and there is a PHY role. Thus a simple Tx<=>Rx crossover between two MACs will (supposedly) not work. Though I've never tried it. Point in case - the PHY is among others supposed to provide loopback on demand. It now seems I will need to investigate this specification in detail, going forward. I would have preferred this being Somebody else's Problem.

 

BTW, NXP manufacturers a network chip that does fit the bill (even though it inflates the BOM,) namely the SJA1105. It is a ethernet switch IC with five [RG]MII interfaces that can be configured for Direct or Reverse mode [RG]MII, individually. 

• https://www.nxp.com/docs/en/data-sheet/SJA1105.pdf

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Scholar
Scholar
389 Views
Registered: ‎08-07-2014

@HW-Designer,

I have changed and updated my reply! Plz chk.

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Adventurer
Adventurer
372 Views
Registered: ‎05-23-2018

Can you limit yourself to a specific Bit-Rate? RGMII is weird that depending on the Bit-Rate, the clocks go either only PHY->MAC or in both directions. If you use strictly 1Gbit, everything is source-synchronous and reasonably easy to get right.

If you can live with 100Mbit-Mode, RMII is the easiest to use since the clock always comes from outside and the control signals behave nearly identical for both directions.

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Scholar
Scholar
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Registered: ‎08-07-2014

@klasha,

RGMII is weird that depending on the Bit-Rate, the clocks go either only PHY->MAC or in both directions. If you use strictly 1Gbit, everything is source-synchronous and reasonably easy to get right.

In RGMII mode, no matter what the bit rate is, for MAC Rx data, clock comes in from PHY to MAC. For MAC Tx data, clock goes out from MAC to PHY. So you have a receive clock and a transmit clock, in opposite directions and both of them must be treated async while constraining the FPGA design.

From the clock point of view, RMII is different from RGMII  such that the clock generated on-board goes to the MAC and the PHY. You do not have a separate tx_clk and rx_clk here.

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Adventurer
Adventurer
263 Views
Registered: ‎05-23-2018

You're right, i remembered that wrong and confused it with the GTXCLK/TXCLK from GMII.

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