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Adventurer
Adventurer
233 Views
Registered: ‎11-27-2010

zynq ultrascale plus + jesd + IBUFDS_GTE4 + partially routed net

Hi,

    board: - zcu102 + vivado 2017.4

refclk_p and refclk_n are routed to qpll0_clk and qpll1_clk via IBUFDS_GTE4 and then i get this error during bitstream generation    

[DRC RTSTAT-1] Unrouted nets: 2 net(s) are unrouted. The problem bus(es) and/or net(s) are
[DRC RTSTAT-2] Partially routed nets: 3 net(s) are partially routed. The problem bus(es) and/or net(s) are
and RFSystem_x/JesdSubSys/gte4main_0/inst/refclk.

if i choose to use UTIL block [refclk_p and refclk_n] and selected IBUFDSGTE, there is no error

surprisingly, in schematic even UTIL block use same IBUFDS_GTE4 primitive. 

 

I still do not understand this error [in both [error and no-error] case , IBUFDS_GTE4 primitive is instantiated in schematic]

Can you please help me on understanding this better?

 

Thanks

 

 

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Moderator
Moderator
191 Views
Registered: ‎11-09-2017

Re: zynq ultrascale plus + jesd + IBUFDS_GTE4 + partially routed net

Hi

Make sure GT lane and Reference clock in same column.

Clock should route from same quad of GT lane or can be routed from north or south qaud.

Regards
Pratap

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