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Participant
Participant
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Registered: ‎11-26-2018

zynq7 rgmii via mio

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Hi,I put a ethernet phy(BCM54616SCOIFBG)on ps_mio,the two ports are connected with RGMII interfaca(HSTL_18),the mio bank is powered by 1.8V,and the ps_mio_vref_501 is powered by half vcc_mio.The tx data/ctrl/clk and rx clk is termanited to half vcc_mio.

The trace length between two ports is about 3700mil,and the skew between all the traces is less than 10mil.

We read the status of the phy from MDC/MDIO.It seems that the chip is working well, and the link-up is shown on the screen,but we can't ping the target ip, package loss 100%.

We used to put this phy on the PL,the HP_DCI port,still HSTL_18,everything is OK,but there is no DCI on ps_mio.

The phenomenon is so weired,is there any SI problem?  According to the ZC706,there is no termination on the rgmii,what should I do? Cut all the terminations on the TX?  or put termination on the RX at fpga side ,just like DCI?

 


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Moderator
Moderator
318 Views
Registered: ‎11-09-2017

Re: zynq7 rgmii via mio

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Hi

Please refer to Xilinx Eval board schematics and board.

Seems that MDC/MDIO working and link is up, i believe issue might not be related from board.

Regards
Pratap

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Moderator
Moderator
319 Views
Registered: ‎11-09-2017

Re: zynq7 rgmii via mio

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Hi

Please refer to Xilinx Eval board schematics and board.

Seems that MDC/MDIO working and link is up, i believe issue might not be related from board.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

View solution in original post

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Participant
Participant
298 Views
Registered: ‎11-26-2018

Re: zynq7 rgmii via mio

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you mean  it's software configuration that cause this problem?

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