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Visitor chao_xilinx
Visitor
84 Views
Registered: ‎01-23-2019

About LCD display in kc705

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I was trying to write some verilog code to drive the LCD display.

However, I realized that our data[3:0] is not connected. For the examples I studied, they all have [7:0] data bus for each character.

How can I work out this? Do you have some working sample code for kc705 FPGA?

Thanks!

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Xilinx Employee
Xilinx Employee
33 Views
Registered: ‎06-21-2018

Re: About LCD display in kc705

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Hi,

If you search online for "16x2 LCD HDL", you'll find example code.
I found one on Opencores written in VHDL that is well documented and this subset written in Verilog:
https://www.quora.com/What-is-the-Verilog-code-to-display-a-character-on-an-LCD-screen-of-the-Spartan-3E-XC3S400-FPGA-kit

KC705 has a 7 pin interface to it. From the XDC file:

 Line 812: set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
 Line 813: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
 Line 814: set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
 Line 815: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
 Line 816: set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
 Line 817: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
 Line 818: set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
 Line 819: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
 Line 820: set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
 Line 821: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
 Line 822: set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
 Line 823: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
 Line 824: set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
 Line 825: set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]

Thanks,
Andres

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1 Reply
Xilinx Employee
Xilinx Employee
34 Views
Registered: ‎06-21-2018

Re: About LCD display in kc705

Jump to solution

Hi,

If you search online for "16x2 LCD HDL", you'll find example code.
I found one on Opencores written in VHDL that is well documented and this subset written in Verilog:
https://www.quora.com/What-is-the-Verilog-code-to-display-a-character-on-an-LCD-screen-of-the-Spartan-3E-XC3S400-FPGA-kit

KC705 has a 7 pin interface to it. From the XDC file:

 Line 812: set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
 Line 813: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
 Line 814: set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
 Line 815: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
 Line 816: set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
 Line 817: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
 Line 818: set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
 Line 819: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
 Line 820: set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
 Line 821: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
 Line 822: set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
 Line 823: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
 Line 824: set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
 Line 825: set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]

Thanks,
Andres

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