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Observer tungho_xilinx
Observer
1,667 Views
Registered: ‎04-08-2017

About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

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Hi guys,

I am having a hard time trying to understand why my IO standards do NOT match the pins that are specified in the attached document, which is part of UG954 (v1.6) user guide and Vivado (2015.4) errors.

When you have time, can you help explain this to me please ??

Thanks,

Have a nice day,
TH

 

ZC706_111127.png
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Xilinx Employee
Xilinx Employee
2,577 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

 

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

 

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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7 Replies
Xilinx Employee
Xilinx Employee
1,401 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Xilinx Employee
Xilinx Employee
1,400 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Xilinx Employee
Xilinx Employee
1,400 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

 

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

 

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Xilinx Employee
Xilinx Employee
1,400 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

 

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

 

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Xilinx Employee
Xilinx Employee
1,463 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

 

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

 

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Highlighted
Xilinx Employee
Xilinx Employee
2,578 Views
Registered: ‎11-30-2007

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

There appears to be an error in Table 1-28 of UG954 (v1.6).  If you view the package file for the XC7Z045-FFG900, you will see the following.  What you will first notice is that the G2 (GPIO_LED_CENTER) and A17 (GPIO_LED_0) pins are located in "High Performance (HP)" IO Banks which means the highest Vcco voltage level they will support is 1.8V.  W21 (GPIO_LED_RIGHT) and Y21 (GPIO_LED_LEFT) pins are located in "High Range (HR)" IO Banks which means the highest Vcco voltage level they will support is 3.3V.

 

Device/Package xc7z045ffg900 9/18/2012 09:53:04                                                                                              
                                                                                                    
Pin   Pin Name                 Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
W21   IO_L20P_T3_11            3                  11    NA            NA                  HR        NA
Y21   IO_L20N_T3_11            3                  11    NA            NA                  HR        NA
G2    IO_L7P_T1_33             1                  33    0             NA                  HP        NA
A17   IO_L18N_T2_AD13N_35      2                  35    0             NA                  HP        NA

 

In the case of the ZC706 board, the Vcco voltage levels are powered by the following voltages:

 

VCCO_11 = VADJ_FPGA (2.5V)
VCCO_33 = 1.5V
VCCO_35 = 1.5V

 

You can confirm this in Table 1-3 of UG954 (v1.6):

 

Table 1-3.jpg

 

You can also download the Master XDC file from the ZC706 Documentation which contains the following:

 

set_property PACKAGE_PIN W21 [get_ports GPIO_LED_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_RIGHT]
set_property PACKAGE_PIN Y21 [get_ports GPIO_LED_LEFT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_LEFT]
set_property PACKAGE_PIN G2 [get_ports GPIO_LED_CENTER]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_CENTER]
set_property PACKAGE_PIN A17 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0]

 

The last issue you have in your screen capture is that you have assigned an IOSTANDARD = LVCMOS18 (implies Vcco=1.8V) for CLK and you have assigned an IOSTANARD = LVCMOS25 (implies Vcco=2.5V) for RESET.  Both CLK and RESET are located in IO Bank 13 so they need to have compatible Vcco voltage levels.

 

You have CLK entering on pin U24.  U24 is a pin that connects to the HDMI CODEC.  So, I don't think that was the clock you intended to use.  You will want to review which clock you are using.  If it is from the PS, you don't provide an XDC constraint because that is a dedicated input clock pin and not configurable.

 

You have RESET entering on pin R27.  R27 is driven by a Push Button so I assume this is correct.  R27 is in IO Bank 13 which is powered by VADJ_FPGA (2.5V).  The Master XDC provides the following constraint:

 

set_property PACKAGE_PIN R27 [get_ports GPIO_SW_RIGHT]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_RIGHT]

 

In summary, you need to adjust your XDC file for GPIO_LED_CENTER and GPIO_LED_0 as well as review your input clock source.

 

I hope this information helps you overcome your issue.

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Observer tungho_xilinx
Observer
1,475 Views
Registered: ‎04-08-2017

Re: About Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit: UG954 (v1.6)

Jump to solution

Hi miker,

Thank you for your reply. I have learnt a lot more today. I have fixed the LED pins. I will work on the clock next. I will read more information from the user guide and reference manual next.

Thanks,

Have a nice day,

TH

 

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