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Visitor derekf66
Visitor
10,671 Views
Registered: ‎06-19-2014

Accessing Clock on VC7203 Eval Board

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Hi,

 

I am using the VC7203 Eval Board and Vivado 2015.1.  I am new to FPGAs and was able to upload a very simple combinational logic program that utilizes the user i/o leds and buttons.

 

I am now trying to create a similarly simple program that uses a clock as an input.  I am trying to use the "Regional Clock" from the Superclock Module on pin K19 but whenever I run it the always@(posedge clk) loop is never run which tells me that the clock is not hooked up right.  The code works fine in simulations.

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Visitor derekf66
Visitor
19,825 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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I finally resolved the issue.  Because I'm new to FPGAs I didn't realize that I had to use both inputs of the differential system clock on pins E19 and E18 and use IBUFGDS instantiation in my code to generate my clock signal.  I thought I had read somewhere that I only needed to use pin E19 if I didn't care about the benefits of a differential clock.

 

Thank you all for your input.

 

 

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9 Replies
Xilinx Employee
Xilinx Employee
10,664 Views
Registered: ‎02-16-2014

Re: Accessing Clock on VC7203 Eval Board

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Hi,

 

If you are looking to simply test any sequenctial logic and clock, why don't you use system clock ?

On Vc7203 board 200 MHz 2.5V LVDS Oscillator is present.

You can directly use this clock to test your logic.

 

Just assign your input clock to FPGA E19 pin and check your sequential logic.

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Xilinx Employee
Xilinx Employee
10,651 Views
Registered: ‎07-23-2012

Re: Accessing Clock on VC7203 Eval Board

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Did you program the superclock module on VC7203?
For details on programming superclock module, please refer to UG847 (Starting the SuperClock-2 Module section).
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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Visitor derekf66
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10,641 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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Hi,

 

Thank you for the replies.  I tried running it with E19 as my clock pin but I'm still not seeing that the clk is working properly.  Since I am using the system clock do I need to add a "create clock" line to my .xdc file?  I've tried both with this line and without it but niether worked.  Is there some other setting I need?

 

I have not started the superclock module because I didn't realize I needed to.  Unfortunately, I do not have the tcl script required because I do not have the SD card.  When I try to download the file online (rdf0272-vc7203-ibert-2015-1.zip) I get an error (I contacted webmaster@xilinx a number of days ago).

 

I'm fine with using the system clock for now, but as I said I am still having trouble with even that.

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Xilinx Employee
Xilinx Employee
10,636 Views
Registered: ‎02-16-2014

Re: Accessing Clock on VC7203 Eval Board

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Hi,

 

Is your design working as expected in simulation?

 

Do you see any warnings or errors in the TCL console regarding the clock?

If you see any, please post here

 

 

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Visitor derekf66
Visitor
10,632 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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Yes the design works perfectly in simulation.  I just reviewed the runme.log files for my last synthesis and implementation runs (without the "create_clock" line in the .xdc file) and there were no warnings or errors.  This run was also using the system clock on pin E19.

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Visitor derekf66
Visitor
10,624 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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I just ran the post-synthesis functional and timing simulations and noticed that those simulations do not work as expected.  My simple circuit is supposed to set the state of an LED at each clock cycle based on the state of a push button.  If I am pushing the button then "led_clock" should turn on at the next clock cycle.

 

The waveform from the post-synthesis simulation shows the clock working but the "led_clock" signal remains low the entire time.  I'm not sure why this would be.

 

Please see the attached schematic and post-synthesis simulation timing waveform.

waveform.png
schematic.png
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Xilinx Employee
Xilinx Employee
10,622 Views
Registered: ‎02-16-2014

Re: Accessing Clock on VC7203 Eval Board

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Hi,

 

Can you share your RTL code and constraints to check on this issue?

 

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Visitor derekf66
Visitor
10,619 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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See attached.  Thank you for your continued support.

 

I should also note that I realized after I posted the waveform that my testbench file had a much higher clock frequency than that which I hope to use.  I did a quick test where I changed the clock period from 10 ns to 100 ns in the testbench file and then my waveform looked as expected.  My original tb file with 10ns clock period is attached.

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Visitor derekf66
Visitor
19,826 Views
Registered: ‎06-19-2014

Re: Accessing Clock on VC7203 Eval Board

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I finally resolved the issue.  Because I'm new to FPGAs I didn't realize that I had to use both inputs of the differential system clock on pins E19 and E18 and use IBUFGDS instantiation in my code to generate my clock signal.  I thought I had read somewhere that I only needed to use pin E19 if I didn't care about the benefits of a differential clock.

 

Thank you all for your input.

 

 

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