UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
712 Views
Registered: ‎03-27-2017

Board Forwarded Clock Multiplied

Jump to solution

Target: VCU118

 

I'm forwarding a clock that is generated on the development board (156.25 MHZ from an SI53340 on-board chip) to two FMC outputs as such:

 

Differential Clock -> IBUFDS -> ODDRE1 -> OBUFDS -> FMC pins

 

Observing the output on the oscilloscope, the frequency seems to be about 2x 156.25 MHz. Switching the clock source to a 125 MHz (on-board SI5335A), the output is 125 MHz confirmed by oscilloscope. 

 

This suggests there is something about the SI53340 chip that multiplies the frequency?

 

Top:

 

module clock_test(
clock_in_p, clock_in_n, clock_out_p, clock_out_n
    );
    
input wire clock_in_p, clock_in_n;
output clock_out_p, clock_out_n;

wire clock_out_ibufds, clock_out_oddr;

IBUFDS #(
.DQS_BIAS("FALSE") // (FALSE, TRUE)
)
IBUFDS_inst (
    .O(clock_out_ibufds), // 1-bit output: Buffer output
    .I(clock_in_p), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
    .IB(clock_in_n) // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

ODDRE1 #(
    .IS_C_INVERTED(1'b0), // Optional inversion for C
    .IS_D1_INVERTED(1'b0), // Optional inversion for D1
    .IS_D2_INVERTED(1'b0), // Optional inversion for D2
    .SRVAL(0) // Initializes the ODDRE1 Flip-Flops to the specified value (1'b0, 1'b1)
)
ODDRE1_inst (
    .Q(clock_out_oddr), // 1-bit output: Data output to IOB
    .C(clock_out_ibufds), // 1-bit input: High-speed clock input
    .D1(1'b1), // 1-bit input: Parallel data input 1
    .D2(1'b0), // 1-bit input: Parallel data input 2
    .SR(1'b0) // 1-bit input: Active High Async Reset
);

OBUFDS #(
)
OBUFDS_inst (
    .O(clock_out_p), // 1-bit output: Diff_p output (connect directly to top-level port)
    .OB(clock_out_n), // 1-bit output: Diff_n output (connect directly to top-level port)
    .I(clock_out_oddr) // 1-bit input: Buffer input
);
    
endmodule

 

 

Constraints:

 

set_property PACKAGE_PIN AW23 [get_ports clock_in_p]
set_property PACKAGE_PIN AW22 [get_ports clock_in_n]

set_property IOSTANDARD LVDS [get_ports clock_in_p]
set_property IOSTANDARD LVDS [get_ports clock_in_n]

set_property PACKAGE_PIN BC9 [get_ports clock_out_p]
set_property IOSTANDARD LVDS [get_ports clock_out_p]

set_property PACKAGE_PIN BC8 [get_ports clock_out_n]
set_property IOSTANDARD LVDS [get_ports clock_out_n]

 

0 Kudos
1 Solution

Accepted Solutions
Community Manager
Community Manager
1,157 Views
Registered: ‎07-23-2015

Re: Board Forwarded Clock Multiplied

Jump to solution

@bfung The Si53340 has the CLK_SEL input connected to Jumper J8. 

You need to have a Jumper on J8 to select the 156.25 MHz clock on CLK1 input of Si53340. If not, you will have the 300 MHz clokc from SI5335A on CLK0 input which is what I believe you are observing. 

 

Insert a jumper on J8 and check. Below from UG1224

 

vcu118_clk.JPG

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
1 Reply
Community Manager
Community Manager
1,158 Views
Registered: ‎07-23-2015

Re: Board Forwarded Clock Multiplied

Jump to solution

@bfung The Si53340 has the CLK_SEL input connected to Jumper J8. 

You need to have a Jumper on J8 to select the 156.25 MHz clock on CLK1 input of Si53340. If not, you will have the 300 MHz clokc from SI5335A on CLK0 input which is what I believe you are observing. 

 

Insert a jumper on J8 and check. Below from UG1224

 

vcu118_clk.JPG

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------