UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer tamqvu
Observer
129 Views
Registered: ‎05-23-2019

Clock Jitter for Clock Wizard

Jump to solution

Where can I get the jitter spec for device Kintex 7 using Clock Wizard PLL?

0 Kudos
1 Solution

Accepted Solutions
102 Views
Registered: ‎01-22-2015

Re: Clock Jitter for Clock Wizard

Jump to solution

@tamqvu 

For many of the Xilinx FPGAs, including the Kintex-7, it is recommended that a low-jitter external clock be brought into the FPGA via clock-capable pins and routed immediately to a PLL or MMCM clock management tile.  With the aide of the Vivado Clocking Wizard, the PLL or MMCM is then configured to produce all clocks for the design. 

As part of the Clocking Wizard configuration, you must specify jitter for the external clock, which is done in the “Clocking Options” tab. 
jitter_in.jpg

After you have finished Clocking Wizard configuration, jitter for each output clock of the PLL/MMCM is automatically reported in the “Summary” tab. 
jitter_out.jpg

In both cases, jitter is a Peak-to-Peak (Pk-Pk) value.  Pk-Pk jitter is a combination of the RMS period-jitter for the clock and a desired value for Bit-Error-Rate (BER).  Generally, we use the conversion that Pk-Pk jitter is 14 times the RMS period-jitter which implies a BER of 1 in 10^12.  For more information, see <this> article.

There is a maximum input jitter specification for the PLL (see Table 42 of Xilinx document DS182).  However, good clock sources have jitter well below this maximum.

Generally, if you properly specify external clock jitter to the Clocking Wizard and your project passes timing analysis then the jitter of your external clock is low enough.  If your project fails timing analysis, then you may need to use an external clock with lower jitter. 

You may also find the discussion of clock jitter in <this> thread to be helpful.

Mark

 

0 Kudos
1 Reply
103 Views
Registered: ‎01-22-2015

Re: Clock Jitter for Clock Wizard

Jump to solution

@tamqvu 

For many of the Xilinx FPGAs, including the Kintex-7, it is recommended that a low-jitter external clock be brought into the FPGA via clock-capable pins and routed immediately to a PLL or MMCM clock management tile.  With the aide of the Vivado Clocking Wizard, the PLL or MMCM is then configured to produce all clocks for the design. 

As part of the Clocking Wizard configuration, you must specify jitter for the external clock, which is done in the “Clocking Options” tab. 
jitter_in.jpg

After you have finished Clocking Wizard configuration, jitter for each output clock of the PLL/MMCM is automatically reported in the “Summary” tab. 
jitter_out.jpg

In both cases, jitter is a Peak-to-Peak (Pk-Pk) value.  Pk-Pk jitter is a combination of the RMS period-jitter for the clock and a desired value for Bit-Error-Rate (BER).  Generally, we use the conversion that Pk-Pk jitter is 14 times the RMS period-jitter which implies a BER of 1 in 10^12.  For more information, see <this> article.

There is a maximum input jitter specification for the PLL (see Table 42 of Xilinx document DS182).  However, good clock sources have jitter well below this maximum.

Generally, if you properly specify external clock jitter to the Clocking Wizard and your project passes timing analysis then the jitter of your external clock is low enough.  If your project fails timing analysis, then you may need to use an external clock with lower jitter. 

You may also find the discussion of clock jitter in <this> thread to be helpful.

Mark

 

0 Kudos