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Adventurer
Adventurer
348 Views
Registered: ‎02-13-2019

Clocks of the Evaluation board KC705

Hi, I'm Jose and I'm a bit new with the use of FPGA.

I have an Evaluation board KC705, and I'd like to know if is possible to generate or create a clock of the frequency I wish. For example, the board has a 200 MHz system clock, but if I'd need 500MHz there exist the possibility of get it? how? any documentation do you recommend for it ?

 

thanks for any help

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7 Replies
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Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎06-21-2018

Re: Clocks of the Evaluation board KC705

Hi jose,

You can find on the board's User Guide (UG810, page 29) an introduction to U45, a Programmable User Clock Source (Si570).

It can be programmed to frequencies from 10 MHz to 810 MHz, using I2C (address 0x5D).

RDF0176 has bitfiles for several Fixed Frequencies or you can create your own bitfile with the Design Files from RDF0175.

Thanks,
Andres

308 Views
Registered: ‎01-22-2015

Re: Clocks of the Evaluation board KC705

@jose09621 

The KC705 evaluation board has a Kintex-7 FPGA.  The 200MHz clock that you mentioned is the system clock for this FPGA.  After this system clock enters the FPGA, we usually route it to a Clock Management Tile (CMT) found inside the FPGA.  The CMT (also called MMCM or PLL) can be setup to create a 500MHz clock (or to create multiple clocks) from the 200MHz clock.

Setting up the CMT to create the 500MHz clock (and other clocks) is best done with the Xilinx IP called the Clocking Wizard, which you can read about in Xilinx document, PG065.

The 500MHz clock created by the CMT can be used inside the FPGA or you can route it out of the FPGA for use elsewhere.  Although clocks created by the CMT are suitable for use inside the FPGA, they may have too much jitter for some uses outside the FPGA.  While you are using the Clocking Wizard to setup the CMT, you will be told how much jitter is present on the 500MHz clock.

Cheers,
Mark

Adventurer
Adventurer
248 Views
Registered: ‎02-13-2019

Re: Clocks of the Evaluation board KC705

@andresb  thanks for your answer. 

 

do you know if I need to do the same process every time the KC705 is powered on?

 

thanks

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Adventurer
Adventurer
243 Views
Registered: ‎02-13-2019

Re: Clocks of the Evaluation board KC705

Mark thanks for answering.
I followed the guide and generated the IP core. For probe it, I had to comment an ODDR module that generated some errors; I implemented a counter of 1 seconds viewing the change in the leds. But is there another way I can know or assess that really is being generated the frequency of 500 MHz?
Additionally, because I have to count 500M to change the value on leds I needed 29 bits (reg variable) and it presented problems meeting timing; I reduced the size of the reg variable to a small size and then the timing problems disappeared.

thanks Mark
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237 Views
Registered: ‎01-22-2015

Re: Clocks of the Evaluation board KC705

@jose09621 

     But is there another way I can know or assess that really is being generated the frequency of 500 MHz?
As you mentioned, the ODDR circuit (see Fig 2-18 in UG903) is the proper way to send a clock out of the FPGA.  -but it is hard to see a 500MHz clock with test equipment.  So, you could use your counter idea to divide the 500MHz clock by 100, giving you a 5MHz toggle-signal.  Then, send this 5MHz toggle-signal out a port of the FPGA so you can view it on an oscilloscope.  Most modern oscilloscopes can accurately display a 5MHz clock.

Mark

Adventurer
Adventurer
233 Views
Registered: ‎02-13-2019

Re: Clocks of the Evaluation board KC705

Thanks for share your knowledge Mark. I really appreciate your help.

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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎06-21-2018

Re: Clocks of the Evaluation board KC705

Jose: regarding using the fixed frequency bitfiles, you would have to load the bitfile every time the board is powered on.

Thanks,
Andres

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