01-25-2011 05:23 AM
Has anyone used Digilent's Atlys board?
Keen on knowing DDR b/w obtained and MIG settings suitable to use that memory.
There's no reference design yet
01-25-2011 11:33 PM
01-31-2011 09:52 AM
Did you manage to use DDR2 on Atlys?
Let me know, I am not sure about buying this board as have no reference design / success stories about DDR2 access besides Agillent user's guide claim ".....tested at 800 MHz...."
01-31-2011 11:31 PM
I never used this board, just seeing other people asking for help. But as I can see it, is all you need for a successful DDR2 implementation is in the docs.
02-01-2011 06:18 AM - edited 02-01-2011 06:35 PM
Their website says "Source code for Atlys DDR2 and SPI Flash memory controller configuration" is available.
I have downloaded the zip file and there's no DDR2 related stuff.
Digillent support says reference design will be available in next quarter.
Hence exploring has anyone got it working with own efforts.
02-01-2011 02:47 PM
I just bought this board and I started playing with it today. I was hoping to use Coregen to interface to the DDR2 ram, but I'm not really sure what I'm doing. Has anyone had any success with using the ram?
02-01-2011 10:09 PM
I looked into MIG
in "Memory Part" selection, DDR2 part on Atlys (MT47H64M16HR-25E) is not listed.
So thats makes us to use "Create custom part" and we enter in the world entering memory timing parameters etc.
In this stage the information fed should be VERY ACCURATE as it will affect correctness and efficiency of generated RTL.
So lot of work stored ahead
02-02-2011 12:22 AM
MTH47H64M16XX-25E is listed for me. I'm just assuming that the 'HR' in the part number doesn't affect the interface. I haven't read through the getting started guides yet but it seems kinda straight forward. I'm kinda disappointed that digilent didn't provide an ise webpack design project that demonstrated the whole board. Their documentation was much better for the Nexys2 board. In the meantime, I got the new picoblaze processor up and running really quick. I also hooked up the HDMI output from the demo program to my TV, kinda disappointing. The picture has all sorts of noisy red lines through it. I hope the RAM can be configured to work better. I'm working on it tomorrow all day, snow day!
02-02-2011 02:29 AM
Yes the DDR2 part appears in ISE 12.3, I was looking into 12.1
Then I guess its a matter of looking into Atlys schematics and provide that info like Drive strength, termination etc to MIG
02-03-2011 07:41 PM
First of all, manual says "The DDR2 device, a Micron MT47H64M16-25E or equivalent [...]". There is no "H" as third character. I assume this is an error in your posting.
Secondly, there is an entry for a memory device called "MT47H64M16XX-25E" in the MIG 3.61 in Coregen 12.4 but it is wrong. If you look up the datasheet of the MT47H64M16-25E, you will see that tRAS is specified as 45 ns for the -25E part and not 40 ns as in MIG. You can see the data in MIG when clicking on "Create custom part". The other parameter seem to be okay, though.
Thus, you will have to create you own corrected memory part in MIG.
The other options can be derived from the manual, the schematics or simply guessed:
Use extended MCB performance range (click to enable)
Frequency: 2.500 ps (400 MHz)
Output drive strength: Full strength (what else at 800 MHz data rate?)
RTT (nominal) ODT: 150 ohms (see e.g. here as we only have one device, i.e. one rank)
DQS# Enable: Enable (we have differential DQS for both bytes of the memory channel as can be seen in the Atlys manual page8: UDQS_P, UDQS_N, LDQS_P and LDQS_N; L/U: lower/upper byte DQS; _P/_N: positive and negated)
High Temp Self refresh rate: disabled (my memory does not operate in conditions > 85 °C; Do you guys know how hot 85 °C is in Fahrenheit? ;-) )
SSTL_Output drive strength: I have no idea. I left it at the default (SSTL_2)
Memory Pin Termination: Calibrated Input Termination (both pins can be found in the schematic and manual)
RZQ location: L6
ZIO location: C2
System clock: differential (isn't this required in the manual?)
Does anyone have ideas for the missing settings? I hope this helps...
02-03-2011 09:53 PM
All these information is very vital and should be in manual.
It boils down to trial-and-error which doesn't make sense when ones buys an "off-the-shelf tested" prto-board !
As board must have got tested for claimed 800MHz DDR2 access, I don't understand why these settings are not there in manual
02-03-2011 10:29 PM
I just took a short look at the Atlys_ManTest3_InitMemTest_Clean EDK project.They're using the MPMC Logicore to generate the memory controller and not the MIG. Furthermore, it seems they operate the DDR2 at 300 MHz there (not 400, i.e. 800 MHz DDR) with a memory part setting of "EDE1116AXX-8E" which not only differs from the Micron memory in the tRAS setting but also tRC. And they use and ODT value of "reserved/50Ohms", not 150.
What's the best setting? And why only 300 MHz?
02-13-2011 05:53 PM - edited 02-13-2011 05:55 PM
gloomy, which clock are you using? The on-board 100 MHz oscillator on the Atlys is single ended. Note that if you want to use a memory frequency higher than the clock you feed in, it's necessary to fiddle with the PLL parameters in the generated files.
Thanks for the tRAS timing tip! I wasn't sure about the ODT value either.
I found the documentation and generated test applications quite baffling (it seems like most people just use the EDK) and am working on a tutorial for using MIG with ISE, targeting the Atlys in particular. While it's not yet complete, I hope that it saves someone some time.
02-13-2011 06:11 PM
I talked with on old professor I had to see if he could help me with the MIG. He suggested I just cough up the money for EDK. How much is a student version of EDK anyways?
02-21-2011 05:00 AM
For those interested in a reference design for the Atlys board that is not EDK oriented,
I am porting the OpenCores OpenRISC ORPSoC for this board (http://opencores.org/openrisc).
Currently I have DDR2, ethernet, SPI and UART working and Linux booting.
Check out http://www.chokladfabriken.org/projects/orpsoc-atlys for source and a prebuilt .mcs binary with Linux.
At the moment I am working on the HDMI output.
05-28-2011 10:44 AM
I'm having alot of issues with MIG/DDR *and* Video at the same time. I can make DDR2 work no problems. Similarly for Video (i.e. XAPP 495). But when i try them together i get no signal on the TMDS ports. It seems something about the IOSTANDARDS set for the DDR causes the video to be optimised out of the design.
I can supply a demo project for anyone who wants to have a look.
05-29-2011 02:49 AM
The problem for anyone else stupid enough to hit the same problem is that the MIG defines DEBUG and the xapp495 output demo has `ifdef DEBUG statement. This causes the video to be non-functional and optimised out. Removing the debug blocks makes everything work.
05-29-2011 03:37 AM
your project sounds very interesting, thanks for this. I've downloaded the sources, jumped to the /doc directory, did a ./configure (which went well). But when I try to 'make pdf' it complains about 'texi2dvi' not found. I've installed tex-live, but I can't find texi2dvi (I'm using pdflatex normally). That's with Ubuntu 10.4. Do you know which package(s) I need to create the documentation?
06-07-2011 01:28 PM
I'm designing for the Atlys board; expect to pick one up in a week or two.
A difference from the reference design is that I'm running the video logic at twice the pixel clock frequency. The reason for doing this is that this frequency is needed anyway for the OSERDES to work and so it eliminates a clock domain. It also eliminates the video FIFO that converts from pixel frequency to twice pixel frequency.
Which reminds me, can't you remove that FIFO by simply putting a circuit to ship DDR pixels at the pixel rate frequency? To do this, one has to get the pixel clock into the fabric (i.e. off of the BUFG clock paths so that it can be used in regular logic). One does this with a toggle, registering at the falling clock, and then take the XOR function between the two registers.
Before I redid the logic so that the system ran at twice the pixel frequency, I redid the HDMI encoder to use 1/3 of the area. This replaces the "encode.v" from XAPP495 with VEncode.vhdl and DISPCNTR.SCH (schematic). The basic idea was to analyze the algorithm mathematically, eliminate redundant logic, and design to the two-output LUT-6 structure of Spartan-6 CLBs. Anyone interested I'll post the files.
07-05-2011 11:34 PM
Did you manage to run DDR2 controller generated from MIG on Atlys? -- what are the MIG settings / parmeters for terminations etc? Can you share those?
What read / write bandwidth you could obtain? - I have been asking these things to Atlys support never got a substantial answer.
07-06-2011 10:26 AM
I haven't tried the memory yet.I found the relevant parameters to be determined by
examination either of the manual or the schematic.
Meanwhile, I'm delaying release of the HDMI encoder until I've made the method
of implementation more accessible as a library part. The efficiency arises from
arranging for pairs of signals to fit into LUT6_2s, and by putting a nice fit into
a CARRY4 for the running disparity.
The running disparity needs a 4-bit counter (as the low bit in the 5-bit implementation
is stuck and so is ignored). One needs to add or subtract constants from -5 to +5 to
it. So it can be thought of as an increment circuit with 4 control signals.
This fits nicely into a slice. The general slice I've created (but not fully tested)
has a single std_logic_vector input that gives the number being incremented
(or loaded), a std_logic_vector(3 downto 0) that controls what operation is
done, a 16-wide string that defines the16 operations (add or load), and an
array of 16 integers that give the constants to either load or add. (To subtract,
you use 2s complement / mess with carry-in).
For the DDR SDRAM, the .xco values I used were:
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_Virtex6_and_Spartan6 family Xilinx,_Inc. 3.7
# END Select
# BEGIN Parameters
# END Parameters
# CRC: 4f566fd2
CORE Generator Options:
Target Device : xc6slx45-csg324
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : DDRSDRAM
No of Controllers : 1
Hardware Test Bench : disabled
Controller Options :
Memory : DDR2_SDRAM
Design Clock Frequency : 2500 ps (400.00 MHz)
Memory Type : Components
Memory Part : MT47H64M16XX-25E
Equivalent Part(s) : MT47H64M16HR-25E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 4(010)
CAS Latency : 5
DQS# Enable : Enable
DLL Enable : Enable-Normal
OCD Operation : OCD Exit
Output Drive Strength : Reducedstrength
Outputs : Enable
Additive Latency (AL) : 0
RDQS Enable : Disable
RTT (nominal) - ODT : 50ohms
High Temparature Self Refresh Rate : Disable
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : CALIB_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended
11-28-2011 11:07 PM
I am using Digilent Atlys board inorder to learn the EDK flow and getting familiar with various IP cores in EDK.
While trying to use UART core, I am stuck in getting the value out from Hyperterminal.
I tried using the 'hello world.c' application and also tried to use a customized IP from whre I am pumping some predefined value onto UART. But nothing show any result. Sometimes I got some junk characters coming but its only with some builds.
Well, can you help me fixing this. At this point I was some clear documentation which can tell me how to use Atlys board inorder to bring up the UART.
I welcome any idea on this problem. Please mark a copy to my below email.
mail id: firstname.lastname@example.org
11-28-2011 11:10 PM
Please start a new thread, possibly in one of the EDK forums.
Have you checked the UART output (between the FPGA and the USB chip) using an oscilloscope?
11-28-2011 11:19 PM
I can see the transmitted data coming out from FPGA (UART-TX) in oscilloscope. Also its timing in terms of UARTframe with baud rate looks fine.
I will start a thread.
05-20-2013 02:46 PM
I need information about using the HDMI port for getting data in and out.I am using atlys spartan 6 FPGA (LXS45). How did you go about it?
Also, I am using ISE webpack 14.5.
05-20-2013 02:56 PM