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Visitor rkutty
Visitor
7,419 Views
Registered: ‎05-18-2011

FMC VADJ HP HR and 7 series

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Hi,

 

A few general questions on FMC-

 

Is all the pins of a FMC connector must have the same IO voltage? VADJ common to all? In otherwords is it possible to have LVCMOS25 AND LVCMOS18 on the same FMC connector (but different banks)? Especially for the 7 series, is mix of HP and HR banks possible? In some forums I read some pins use "voltages from the FMC" - is there a way to know about these pins- how they will be idenitifed?

 

Also, for a particular row (say G), is it safe to assume for all the Gx pins, clock (G6 & G7) will be common? I mean, the pins are on the same local clock net? In ortherwords, is there any relationship between the clock capable pins & other pins on the FMC? Also, is there a pin assignment/selection rule on FMC?

 

Thanks,

Rejeesh

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Visitor rkutty
Visitor
9,417 Views
Registered: ‎05-18-2011

Re: FMC VADJ HP HR and 7 series

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Hi,

 

Thanks for the quick reply. I understand the FMC part- but not sure how that maps to actual pins on the FPGA (at least I couldn't find it on the spec.). I admit that I will have to read it multiple times to understand it fully and I am not there yet.

 

As a specific example, the VC707 board both are HP FMC connectors and both carry HP pins (no HR). If HP pins are IO limited to only 1.8v, what about a daughterboard that requires 2.5v IO standards? I am trying to understand the guidelines of the mother board (in this case VC707) so that I could pick the pins on the FMC accordingly. Or is my understanding wrong (I am a bit confused)?

 

If I put it shortly- what are the guidelines for pin assignments between FMC & FPGA on the mother (or main) board? How a person designing the daughter board make sure compatibility across all future "main/mother" boards?

 

BTW, Is there an IP that reads the EEPROM and adjusts the VADJ rails accordingly?

 

Thanks,

Rejeesh

 

 

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Xilinx Employee
Xilinx Employee
7,417 Views
Registered: ‎01-03-2008

Re: FMC VADJ HP HR and 7 series

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You should really pick up a copy of the VITA 57.1 spec as this defines the interface and answers all of your questions.

 

The VADJ supply is the VCCO for tha LA and HA busses and the VIO_B_M2C supply (from the mezzanine card) is the supply for the HB bus.

 

For the 6 Series the carrier cards (SP601, SP605, ML605) had a fxied 2.5V VADJ and FMC mezzanine cards would connect the VADJ to the VIO_B_M2C supply.

 

For the 7 Series the carrier cards will support an adjustable VADJ for LA and HA busses.  Per the FMC standard the carrier card is supposed to read the EEPROM on the mezzanine card and if the VADJ level is acceptable then it will raise the VADJ supply and if it isn't then it will be off.

------Have you tried typing your question into Google? If not you should before posting.
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Visitor rkutty
Visitor
9,418 Views
Registered: ‎05-18-2011

Re: FMC VADJ HP HR and 7 series

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Hi,

 

Thanks for the quick reply. I understand the FMC part- but not sure how that maps to actual pins on the FPGA (at least I couldn't find it on the spec.). I admit that I will have to read it multiple times to understand it fully and I am not there yet.

 

As a specific example, the VC707 board both are HP FMC connectors and both carry HP pins (no HR). If HP pins are IO limited to only 1.8v, what about a daughterboard that requires 2.5v IO standards? I am trying to understand the guidelines of the mother board (in this case VC707) so that I could pick the pins on the FMC accordingly. Or is my understanding wrong (I am a bit confused)?

 

If I put it shortly- what are the guidelines for pin assignments between FMC & FPGA on the mother (or main) board? How a person designing the daughter board make sure compatibility across all future "main/mother" boards?

 

BTW, Is there an IP that reads the EEPROM and adjusts the VADJ rails accordingly?

 

Thanks,

Rejeesh

 

 

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Xilinx Employee
Xilinx Employee
7,410 Views
Registered: ‎01-03-2008

Re: FMC VADJ HP HR and 7 series

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In the case of 7 Series HP bank connected to a FMC card, the range VADJ/VCCO will be 1.2-1.8V and for a HR bank 1.2-3.3.V  In the case of LVDS operation, the VCCO must be 1.8V for the HP banks and 2.5V for the HR banks.

 

In order to have maximum compatibility, I would strongly suggest the use of level translators on the FMC mezzanine card for all control/slow speed signals and an adherence to the FMC specification that calls for the LA busses to be populated first, followed by the HA and then the HB busses.

 

> BTW, Is there an IP that reads the EEPROM and adjusts the VADJ rails accordingly?

We will be releasing a design that does this and there will also continue to be a fixed level option for users that don't want full conformance to the FMC specification.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Adventurer
Adventurer
7,395 Views
Registered: ‎04-13-2010

Re: FMC VADJ HP HR and 7 series

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>> BTW, Is there an IP that reads the EEPROM and adjusts the VADJ rails accordingly?

 

> We will be releasing a design that does this and there will also continue to be a

> fixed level option for users that don't want full conformance to the FMC specification.

 

Do the Xilinx FMCs support the EEPROM now? Last time I looked the boards came with empty EEPROMs and support was not able to provide any kind of FRU description.

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