UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor tafr8517
Visitor
10,655 Views
Registered: ‎06-25-2013

Generation of 4 Phase Shifted clock Signals from DCM

Hello,

 

I am a new user to VHDL and programming FPGAs. I'm working on a Spartan-3E using ISE webpack 14.6. I would like to generate 4 phase shifted signals, each at 32Mhz, using the on board DCM. Initially I would like to be able to see the behavior of the 4 signals during a behavioral simulation in ISim. I've followed a few tutorials that used the IP (CORE generator and design) but I faced my lack of experience when i tried to write a simple code to preform the action described earlier. Also attached is a image of what i would like to preform, except the image only contains 3 signals rather than 4.

 

If anyone could suggest any example code or tutorials it would be greatly appreciated! 

imgf0001.png
0 Kudos
6 Replies
Scholar austin
Scholar
10,653 Views
Registered: ‎02-27-2008

Re: Generation of 4 Phase Shifted clock Signals from DCM

t,

 

Not so hard.  The 3E had at least 4 DCM's, and one could drive all 4 with a single clock, and have each DCM drive its own BUFG clock tree (also come back to each respective DCM for the feedback path for 0 phase error on each).  At configuration time, the phase of each clock is defined, and loaded as part of the bitstream.  If you wish to change it, you change the attributes, and regenerate the bitstream.  If you wish to dynamically shift each phase, you can do that too, but you will need to create the necessary controls to do that with the phase shift controls of the DCM_Advanced primitive.

 

Oh, and the original clock used to input to the 4 DCM's is  a 5th phase one can use anywhere for anything.


Each DCM is programmed to provide the phase shift desired.  If it is as simple as 0, 90, 180 and 270- derees, that is available from a single DCM, with no work whatsoever -- clock in, 4 phases out, each on its own output to each of four BUFG to be used wherever needed anywhere on the die.  All outputs of the DCM may be used, all at once.  So, if the fixed features work, don't do anything more -- just use it as it.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor tafr8517
Visitor
10,644 Views
Registered: ‎06-25-2013

Re: Generation of 4 Phase Shifted clock Signals from DCM

Thank you Austin for the quick replay!

 

I've been reading though the documentation for the DCM is there a resource that is available which is more applicable to implementing DCM controls into a VHDL code?  As a proof of concept I found/modified a VHDL code that acts as a counter. However, to learn how to properly use DCM I want to phase shift a second counter and run each channel at 32MHZ.

 

Here is the code I started with:

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity counter is

Port ( CLOCK : in STD_LOGIC;

DIRECTION : in STD_LOGIC;

COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));

end counter;

 

architecture Behavioral of counter is

signal count_int : std_logic_vector(3 downto 0) := "0000";

begin

process (CLOCK)

begin

if CLOCK='1' and CLOCK'event then

if DIRECTION='1' then

count_int <= count_int + 1;

else

count_int <= count_int - 1;

end if;

end if;

end process;

 

COUNT_OUT <= count_int;

end Behavioral;

 

My modified code:

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

----------------------------------------------------------------------------------

entity counter is

    Port ( clk0 : in  STD_LOGIC;

           clk90 : in  STD_LOGIC;

           DIRECTION0 : in  STD_LOGIC;

           DIRECTION90 : in  STD_LOGIC;

           COUNT_OUT0 : out  STD_LOGIC_VECTOR (3 downto 0);

           COUNT_OUT90 : out  STD_LOGIC_VECTOR (3 downto 0));

end counter;

----------------------------------------------------------------------------------

architecture Behavioral of counter is

----------------------------------------------------------------------------------

signal count_int0 : std_logic_vector(3 downto 0) := "0000";

signal count_int90 : std_logic_vector(3 downto 0) := "0000";

begin

process (clk0)

begin

                if clk0='1' and clk0'event then

                                if DIRECTION0='1' then

                                                count_int0 <= count_int0 + 1;

                                else

                                                count_int0 <= count_int0 - 1;

                                end if;

                end if;

end process;

COUNT_OUT0 <= count_int0;

process (clk90)

begin

                if clk90='1' and clk90'event then

                                if DIRECTION90='1' then

                                                count_int90 <= count_int90 + 1;

                                else

                                                count_int90 <= count_int90 - 1;

                                end if;

                end if;

end process;

COUNT_OUT90 <= count_int90;

end Behavioral;

0 Kudos
Scholar austin
Scholar
10,641 Views
Registered: ‎02-27-2008

Re: Generation of 4 Phase Shifted clock Signals from DCM

 

t,

 

You don't need to write anything to get your phases from the DCM.  Don't know why you are doing anything at all with counters:  it is all done for you in the DCM.  You are working to hard on something that is already there.  Just use it.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Visitor tafr8517
Visitor
10,637 Views
Registered: ‎06-25-2013

Re: Generation of 4 Phase Shifted clock Signals from DCM

I appreciate you taking the time to help me!

 

I had a feeling that was what I was doing. I'm going to step back and try to stop over thinking it. Also the counter's clocks were what i wanted to apply DCM to but applying it was where I was struggling.

0 Kudos
Highlighted
3,863 Views
Registered: ‎03-09-2016

Re: Generation of 4 Phase Shifted clock Signals from DCM

Hi tafr8517,

 

I am completely new to FPGAs and trying to do the same. Implement two phase shifted clock using DCMs. If you have been able to implement the same can you help me out for Spartan 3E board (Basys 2).

 

Thanks,

Sourav

Tags (2)
0 Kudos
Teacher muzaffer
Teacher
3,834 Views
Registered: ‎03-31-2012

Re: Generation of 4 Phase Shifted clock Signals from DCM

spartan 3 dcm already supports a clk90, clk180 & clk270 outputs.
Are these enough for your purposes? If not, what phases do you need?
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos