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16,475 Views
Registered: ‎03-10-2009

ML506 Ethernet MAC: cannot get example design to work with ISE.

I've been working at this for quite a while now and as a last resort I'm coming to these forums for help.  I'm trying to get the example design included in the Virtex5 Tri-mode Ethernet MAC to work on the ML506 using the ISE.  The IP core has been configured to use MII with only one MAC, and no flow control.  I've been able to get the physical interface on by sending the PHY_RESET signal that is needed (asserted low) but undocumented.  I've very minimally modified the code and constraints.  So, here are the very few steps I have taken to run the Ethernet MAC example design (address swap):

 

example_design.vhd, after line 143:

PHY_RESET : out std_logic

 

example_design.vhd, after line 323:

PHY_RESET <= not reset_i;

 

In the constraints file, I commented out the following lines:

# MII Logic Standard Constraints
#INST "mii_txd_0<?>"      IOSTANDARD = LVTTL;
#INST "mii_tx_en_0"       IOSTANDARD = LVTTL;
#INST "mii_tx_er_0"       IOSTANDARD = LVTTL;
#INST "mii_rxd_0<?>"      IOSTANDARD = LVTTL;
#INST "mii_rx_dv_0"       IOSTANDARD = LVTTL;
#INST "mii_rx_er_0"       IOSTANDARD = LVTTL;
#INST "mii_tx_clk_0"      IOSTANDARD = LVTTL;
#INST "mii_rx_clk_0"      IOSTANDARD = LVTTL;
#INST "mii_tx_clk_0"      IOSTANDARD = LVTTL;

 

And added the following:


NET  RESET                          LOC="V8";    # Bank 18, Vcco=3.3V, No DCI, south sw
NET  MII_COL_0                    LOC="B32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  MII_CRS_0                    LOC="E34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20    
NET  MII_RX_CLK_0               LOC="H17";   # Bank 3, Vcco=2.5V, No DCI                         
NET  MII_RX_DV_0                LOC="E32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20    
NET  MII_RXD_0<0>             LOC="A33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20    
NET  MII_RXD_0<1>             LOC="B33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20    
NET  MII_RXD_0<2>             LOC="C33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20    
NET  MII_RXD_0<3>             LOC="C32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  MII_RX_ER_0                LOC="E33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  MII_TX_CLK_0              LOC="K17";   # Bank 3, Vcco=2.5V, No DCI
NET  MII_TX_EN_0                LOC="AJ10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  MII_TXD_0<0>             LOC="AF11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  MII_TXD_0<1>             LOC="AE11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  MII_TXD_0<2>             LOC="AH9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  MII_TXD_0<3>             LOC="AH10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  MII_TX_ER_0                LOC="AJ9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors 
NET PHY_RESET                LOC = "J14";

 

These are the only steps I have taken and I still cannot get the example design to work.  Has anybody had similar problems?  Any solutions? If any more config details are needed, I'd be more than happy to supply them.  I didn't want to spam the topic with info that may not be needed.

Message Edited by chrisjmichael on 03-10-2009 08:17 PM
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38 Replies
Visitor zzgrrr
Visitor
16,450 Views
Registered: ‎03-04-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

what is your meaning? Is there a physical link error or a function error ?

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16,433 Views
Registered: ‎03-10-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I am not sure what type of error it is.  After programming the Virtex5 on the ML506, the PHY is definitely working because the lights are on, and the RX light flashes when I send a packet.  However, the example design's address swap module should send a packet back upon receiving one and this is not happening.  I'm sure the problem is not physical since the web server demo distributed with the ML506 works fine when loaded.
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Visitor zzgrrr
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16,405 Views
Registered: ‎03-04-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I've got the example design to work on board ml507, but  I can see nothing wrong on the details you've shown.You may use chipscope to exam the project.

In fact, I encounted the same problem as you when I tried to use GMII on board ml507 and I'm still confusing.

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Xilinx Employee
Xilinx Employee
16,392 Views
Registered: ‎11-28-2007

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.


chrisjmichael wrote:
I am not sure what type of error it is.  After programming the Virtex5 on the ML506, the PHY is definitely working because the lights are on, and the RX light flashes when I send a packet.  However, the example design's address swap module should send a packet back upon receiving one and this is not happening.  I'm sure the problem is not physical since the web server demo distributed with the ML506 works fine when loaded.

How did you send packet to ML506 and check loopbacked packet?

 

Did you turn on the auto-negotiation on your packet generator? If yes, did it auto-negotiate the link to 10/100M?

 

The example design has other IO pins that don't exist in your UCF? What did you with them?

 

Would it be possible for you to attach your current design so other people with the same board can try it out?

 

Cheers,

Jim

 

Cheers,
Jim
16,350 Views
Registered: ‎03-10-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Thanks for taking the time out Jim!  Here are the answers to all of your questions:

 


@jimwu wrote:
How did you send packet to ML506 and check loopbacked packet?

Did you turn on the auto-negotiation on your packet generator? If yes, did it auto-negotiate the link to 10/100M?

 

The example design has other IO pins that don't exist in your UCF? What did you with them?

 

Would it be possible for you to attach your current design so other people with the same board can try it out?

 

Cheers,

Jim

 


 

 

I sent the packet to the ML506 by connecting it to my laptop via RJ45.  I disable wireless and do a simple command like "ping www.yahoo.com".  I am sure that a packet is being sent to the ML506 because the RX light blinks as soon as I enter the ping command. I'm using WireShark from my laptop to check the packets I'm sending and receiving.  As confirmed by the indication lights on the ML506 and the traffic statistics on WireShark, packets are being sent from my PC to the ML506, but the packets are not being sent from the ML506 to my PC as they should.

 

Autonegotiation is turned on using my laptop, but the connection doesn't authenticate immediately for some reason.  I've adjusted most configuration parameters in my driver, still had no luck.  I did find a way to get it to work, but I'm not exaclty sure why it works.  When I turn on the ML506, I plug it in via RJ45 into a nearby hub.  The ML506's 10M connection light comes on.  I unplug it, and plug it back into my laptop.  A 1G connection is now established.  It seems to work fine from here.  I've tested the connection by running the web server demo that comes packaged with the ML506.  The demo works perfectly, I can access it from my PC via RJ45 just fine.  When I load the example design, a 1G link is established.

 

I have handled the I/O that the example design has by grounding all inputs and setting all outputs to 'open'.  These signals are all statistics and flow control signals that are not used in the generated code.

 

I am attaching all the vhd files as well as my UCF.   I've been working on this for quite some time, so if there is any additional information you need please let me know.  One config detail off hand that you may be curious about is the jumper J20.  It sets the value of Vcco for banks 11 and 13.  I have left the double jumper at position 1, which sets the Vcco to 3.3V.

 

Again, thanks for your help.

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Xilinx Employee
Xilinx Employee
16,342 Views
Registered: ‎11-28-2007

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I will try out your design when I get a chance. But since you mentioned that the TEMAC is set to MII mode, which is for 10/100M link. It won't work if the link between the board and your laptop is auto-negotiated to 1G. One thing you can try is to force the NIC on your laptop to be 100Mb full duplex.

 

Cheers,

Jim

Cheers,
Jim
16,335 Views
Registered: ‎03-10-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Jim, Thanks a million!

 

I changed the settings in my driver to 100Mb full duplex just as you said and everything worked wonderfully!  Thanks again to you and zzgrrr.  So, the design I posted above should work on the ML506 granted everything on the packet generation side is in order.

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16,004 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I created a core with EMAC0, GMII (1000 MB/s) and no flow control. I made the changes mentioned at the beginning of this thread in regards to the PHY_RESET. I attached the RESET to an external DIP SW (GPIO_DIP_SW8). When I hit the switch out of reset (high to low), I see the ethernet status lights blink once. The status lights are the ones found on the board indicating communication status. I do not see the link or data on my laptop's NIC turn on at all.

 

I am using a Virtex 5 5vsx50tff1136-1.

 

I attached a zip file with the EDK project core files, log files for the build and coregen attributes for the build. 

 

Any suggestions to debug this issue would be great.

 

 

Thank you,

Vince

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15,880 Views
Registered: ‎03-10-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Hey Vince,

 

I have the same problem you have.  I have no explanation for it and haven't done much research as to why it happens, but I have found a work around.  I originally thought the problem had to do with auto switching not working, so I picked up an old 10M hub I had lying around and plugged the ML506 right to it.  Once I noticed that the MAC connection lights lit up, I unplugged the cable from the hub and back into my laptop.  Weirdly enough, the connection was established.  I have to do this every time I restart the ML506.  Plug the patch cable into the hub for a second, then unplug it and plug it in to my laptop.  Perhaps somebody with a little more knowledge of the PHY can enlighten us.

 

Good luck,

Chris.

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10,949 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Hey Chris, 

 

Thanks for the reply!

 

I got the PHY to auto negotiate. It was a bad jumper on the board (who would of figured :o ). I am still unable to get the loopback example working. I see the RX light blink when I send a frame. However, the TX light never blinks. It is possible the elements driving the TX is improperly connected, or a timing contraint is not met.

Any guidance would be appreciated! I attached a file with the project.

Thank you,
Vince

Message Edited by vincekoskesh@hotmail.com on 03-30-2009 08:45 PM
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Visitor dpavli
Visitor
10,780 Views
Registered: ‎04-02-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Hello,

 

I am also trying to implement the "ethernet example design", actually on a ML507 board (Virtex-5 FXT, XC5VFX70T-1136-1) but had no luck with succeeding.

 

The PHY obviously auto negotiates, since I have connected the ML507 board to my computer's gigabit ethernet NIC and while operating the LEDs "UP" and "1000" light.

 

When I try to ping some address (after disabling every other PC's NIC) the RX LED on the ML507 board lights, but there is no response as expected from the address-swap module and the TX LED does not blink at all. Wireshark confirms there was no response from ML507.

 

I have tryed both GMII and SGMII and decided to try to run it with SGMII since the board generates the 125MHz clock for SGMII when properly set with the dipswitch at the bottom and also because if one day I will need to route my own board there will be less work with SGMII.

 

However, first I need to get the address-swap module to work and currently I ran out of ideas. I have noticed that the example design's UCF file does not describe the TXN,TXP,RXN and RXP connections. If I try to set them manually as follows:

 


#INST "eth_TXP_0" LOC = "M2";
#INST "eth_TXN_0" LOC = "N2";
#INST "eth_RXP_0" LOC = "N1";
#INST "eth_RXN_0" LOC = "P1";

 

then the PAR can not successfully route the design but without those instantiations I am not sure how the design should work, since it would not be specified where the TX and RX pairs get connected and routed.

 

The ones that did succeed with the example design, did you specify any other constraints? I tryed to help myself with this guide:http://www.xilinx.com/products/boards/ml505/docs/ml505_sgmii_design_creation.pdf

 

Since I am not an experienced FPGA designer, any help would be appreciated.

 

Thank you and Best regards,

D.Pavliha

 

 

 

 

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10,757 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I was looking at my HDL it may be  the manner the GTX clock is generated. This a code snippet from how my clock is generated:

    -- Generate 125MHz (gtx_clk) and 200MHz (ref_clk)
    clk125_dcm : DCM_BASE
    generic map (
     CLKFX_DIVIDE   => 4,
     CLKFX_MULTIPLY => 5)
    port map
    (CLKIN      => clk,
     CLK0       => clk_fb_emac1,
     CLK180     => open,
     CLK270     => open,
     CLK2X      => ref_clk_bufg,
     CLK2X180   => open,
     CLK90      => open,
     CLKDV      => open,
     CLKFX      => gtx_clk_1_i,
     CLKFX180   => open,
     LOCKED     => dcm_locked,
     CLKFB      => clk100_emac1,
     RST        => rst);

    fb_bufg      : BUFG port map (I => clk_fb_emac1, O => clk100_emac1);
  
    gtx_clk_bufg : BUFG port map (I => gtx_clk_1_i, O => gtx_clk);
  
    refclk_bufg  : BUFG port map (I => ref_clk_bufg, O => ref_clk);
 

It is derived from the 100MHz DIP Switch Settings for Super Clock Generator (SW6)
Switch Setting
1 (N0) OFF
2 (N1) OFF
3 (N2) ON
4 (M0) ON
5 (M1) ON
6 (M2) OFF
7 (SEL1) ON
8 (SEL0) OFF
 

Any suggestions?

 

Thank you,
Vince

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10,755 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

what is the difference between:

1)NET  PHY_TXC_GTXCLK       LOC="J16";   # Bank 3, Vcco=2.5V, No DCI
2)NET  PHY_TXCLK            LOC="K17";   # Bank 3, Vcco=2.5V, No DCI

 

Thank you,

Vince

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Visitor dpavli
Visitor
10,742 Views
Registered: ‎04-02-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I believe that GTXCLK is the clock the designer needs to supply to the TEMAC core, while the TXCLK and RXCLK are clocks generated by the PHY. Someone please correct me if I'm wrong.

 

As for my project I have successfully implemented and tested the TEMAC core into my design and am now able to receive and send data over Ethernet. 

 

However, there are still two things that concern me:

 

1.) Why can the Client interface be just 8-bit wide using all the interfaces but Ethernet-1000X? I am using SGMII, so I am stuck 8 bits of data width.

 

2.) Occasionally my design's transmitter starts flooding the network with strange data; WireShark detects it as:


MAC SRC: aa:bb:cc:dd:ee:ff   
MAC DEST: 01:80:c2:00:00:01   
PROTOCOL: CTRL   
DESTINATION: Spanning-tree-(for-bridges)_01               
BYTES: 60        

 

This occurs always when trying to implement a PLL-ADV structure (I need some custom clocks) and also randomly (I do not know the cause yet). Maybe anyone recognizes the problem and could provide me a hint?

Thank you and best regards,
D.Pavliha

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10,739 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

dpavli,

 

The GTXCLK pin is it an input? What does that pin connect to on the FPGA? The TXCLK would obliviously connect to the PHY TXCLK pin. Correct?

 

Have you tried simulating your design? It looks like MAC control packet to me.

 

Thank you,

Vince

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10,733 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

To what would I connect:

NET  PHY_TXC_GTXCLK       LOC="J16";   # Bank 3, Vcco=2.5V, No DCI

for a GMII implementation?

 

Thank you,

Vince

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Visitor dpavli
Visitor
10,733 Views
Registered: ‎04-02-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Try looking at the schematics for the 125MHz clock from the "Super Clock Generator" IC... or maybe using a PLL to generate a 125MHz clock from 100MHz (that will be less accurate, however).

 

MAC control packet? Huh, why do you think does it get produced anyway?

 

Thank you
D.

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10,724 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

dpavli,

 

You may have Flow control Enabled on your design.

 

I generated a 125 Mhz and a 200 Mhz with a DCM fead 100Mhz.

 

Can you show me your design? I am having some difficulty with the FPGA sending back information. I have a feeling it has to do with the TX clock.

 

Thank you,

Vince

 

 

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Visitor dpavli
Visitor
10,721 Views
Registered: ‎04-02-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

My design uses SGMII and is based on this guide:

 

http://www.xilinx.com/products/boards/ml505/docs/ml505_sgmii_design_creation.pdf

 

 

 

The constraints that may concern you are:

 

    INST "*GTX_DUAL_1000X_inst?GTX_1000X?tile0_rocketio_wrapper_gtx_i?gtx_dual_i" LOC = "GTX_DUAL_X0Y4";
    INST "MGTCLK_N" LOC = "P3";
    INST "MGTCLK_P" LOC = "P4";
    NET "PHY_RESET_0" LOC = J14; # ML505 PHY Reset 

 

Hope this helps,

D.P.

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11,806 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

D.P.,

 

Try this:

 

# Place the transceiver components. Please alter to your chosen transceiver.
INST "*GTP_DUAL_1000X_inst?GTP_1000X?tile0_rocketio_wrapper_i?gtp_dual_i" LOC = "GTP_DUAL_X0Y3";
#INST "MGTCLK_N" LOC = "P3";
#INST "MGTCLK_P" LOC = "P4";
NET "MGTCLK_N_pin" LOC = "P3";
NET "MGTCLK_P_pin" LOC = "P4";

Net TXP_0_pin LOC = M2;
Net TXN_0_pin LOC = N2;
Net RXP_0_pin LOC = N1;
Net RXN_0_pin LOC = P1;

 

Take care,

Vince

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11,803 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

D.P.,

 

I appologize. IT should be GTP_DUAL_X0Y4

 

Vince

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Visitor egueutier
Visitor
11,762 Views
Registered: ‎04-09-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I just browse your various exchanges on Ethernet ML506 and ML507 boards.
And your knowledge of this subject can probably unlock my problem ...

 

I try to implement the example design with the block "address_swap_module_8" on the map ML510 (Virtex-5 fx130T).
I use RGMII interface.
I have taken the block (RMII_example_design) generated by the core and made some changes:

 

- GTX_CLK_0 clock (125 MHz) from a DCM driven by the 100 MHz clock of the card:
     -------------------------------------------------- ----------------------
     - REFCLK used for primitive RGMII IODELAYCTRL - Need to supply a 200MHz clock
     -------------------------------------------------- ----------------------
     -- refclk_ibufg: IBUFG port map (I => REFCLK, O => refclk_ibufg_i) -- modif
     -- refclk_bufg: BUFG port map (I => refclk_ibufg_i, O => refclk_bufg_i) -- modif
     refclk_bufg_i <= CLK_200M - modif


- Refclk_bufg_i clock (200 MHz) is also from the DCM
     -------------------------------------------------- --------------------
     -- Stop the tools from automatically adding in a BUFG on the
     -- GTX_CLK_0 line.
     -------------------------------------------------- --------------------
     -- gtx_clk0_ibuf: IBUF port map (I => GTX_CLK_0, O => gtx_clk_0_i) -- modif
     gtx_clk_0_i <= clk_125M - modif


- PHY_RESET ouput was added

 

- Elements of chipscope were added in order to see internal signals.

 


Some changes at the Core of ucf (cf OWS_00-00.ucf of zip)

 

- CONFIG PART = 5vfx130tff1738-2 (# CONFIG PART = 5vsx50tff1136-1, by default, why ?)

 

- Standard Logic RGMII Constraints in comments:
     # INST "rgmii_txd_0 <>" IOSTANDARD = HSTL_I;
     # INST "rgmii_tx_ctl_0" IOSTANDARD = HSTL_I;
     # INST "rgmii_rxd_0 <>" IOSTANDARD = HSTL_I;
     # INST "rgmii_rx_ctl_0" IOSTANDARD = HSTL_I;
     # INST "rgmii_txc_0" IOSTANDARD = HSTL_I;
     # INST "rgmii_rxc_0" IOSTANDARD = HSTL_I;

 

- Similarly RGMII Logic Placement Example

 

- Added design Nets:
     NET RGMII_TXD_0 <0> LOC = "AR33";
     NET RGMII_TXD_0 <1> LOC = "AP32";
     NET RGMII_TXD_0 <2> LOC = "AR32";
     NET RGMII_TXD_0 <3> LOC = "AN31";
     NET RGMII_TX_CTL_0 LOC = "AP31";
     NET RGMII_TXC_0 LOC = "M26";

     NET RGMII_RXD_0 <0> LOC = "AJ32";
     NET RGMII_RXD_0 <1> LOC = "AJ33";
     NET RGMII_RXD_0 <2> LOC = "AK33";
     NET RGMII_RXD_0 <3> LOC = "AM33";
     NET RGMII_RX_CTL_0 LOC = "AN33";
     NET RGMII_RXC_0 LOC = "J17";
     NET clk_ML510 LOC = "L29";
     NET RESET LOC = "J15" # FPGA_CPU_RESET_B
     NET PHY_RESET LOC = "AK32";


Synthesis and placement / routing are ok. The jumpers of the ML510 are RGMII configuration.
The auto-negotiation is enabled on the generation of packets at the NIC of the PC.

 

On the map, the LEDs "DUPLEX" and "LK/1000 are well lit. The Led "RX" flashes when receiving packages.
However, nothing in the LED "TX", no response from the ML510 and nothing on Wireshark.

 

At Chipscope level, we see:
- Clock gtx_clk_0_i                                 ok
- Clock RGMII_RXC_0 (from PHY)        ok
- Ll_clk_0_i clock (output TEMAC)        ok
- RGMII_TXC_0 clock (from the PHY)   ok

 

- RGMII_RXD_0 the bus is always the value "D". ?????  ko

- RGMII_RX_CTL_0 is always the low state.       ?          


Is there an additional element to configure, not to forget ?
Others signals could be interesting to spy on chipscope ?
Is it because the gtx_clk_0 clock comes directly from a DCM (xilinx warning)?
Has anybody had similar problems?  Any solutions?

 

The "Ml510_bsb2_std_ip_addition" application works well on my card (SGMII interface and clock GTX from a DCM).
I tried in MII (10/100 Mb) and SGMII but also results ko.

 


Thanks for taking the time to read me and maybe solve my problem.
If any more config details are needed, I can supply them.

 

 

Best Regards

 


Eric

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11,757 Views
Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

- CONFIG PART = 5vfx130tff1738-2 (# CONFIG PART = 5vsx50tff1136-1, by default, why ?)

 

 To my knowledge:

 5vfx130tff1738-2 is the FPGA specification, coregen should place the correct string dependng on how you configured it

 

On the map, the LEDs "DUPLEX" and "LK/1000 are well lit. The Led "RX" flashes when receiving packages.
However, nothing in the LED "TX", no response from the ML510 and nothing on Wireshark. 

 

 To my knowledge: 

 I am in the same boat. I assume we need to initialize the core. This is generally done by setting some registers that do not have default values for the core or need to have their enable bit set. This can be done via micorblaze or a packet to the MDIO.I have not tryed this but if you get it working please let me know :-)

 

Others signals could be interesting to spy on chipscope ?

 

 To my knowledge: 
Look at the valid signals and the other signals needed to be driven by the client and the signals coming out of the hard MAC.

 

Is it because the gtx_clk_0 clock comes directly from a DCM (xilinx warning)?

 

 To my knowledge: 

Yes. There is an app node that has this done. app node is xapp957 on the xilinx website.

 

Has anybody had similar problems?  Any solutions?

 

 To my knowledge:  

 I'm in the same boat :-)

 

 Let me know of your progress.

 

Thank you and good luck,

Vince

Message Edited by vincekoskesh@hotmail.com on 04-23-2009 10:24 AM
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Visitor egueutier
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Registered: ‎04-09-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

 

Thanks Vince.

 

On the map, the LEDs "DUPLEX" and "LK/1000 are well lit. The Led "RX" flashes when receiving packages.
However, nothing in the LED "TX", no response from the ML510 and nothing on Wireshark. 

 

 To my knowledge: 

 I am in the same boat. I assume we need to initialize the core. This is generally done by setting some registers that do not have default values for the core or need to have their enable bit set. This can be done via micorblaze or a packet to the MDIO.I have not tryed this but if you get it working please let me know :-)

 

We need inevitably to access PHY registers for RGMII interface via MDIO or microblaze ? 

I thought it was more SGMII and 1000BASE-X PCS / PMA  interfaces ?
The MDIO management option is not offered by the core for RGMII interface. 

which interface do you use ?

 

 

Others signals could be interesting to spy on chipscope ?

 

 To my knowledge: 
Look at the valid signals and the other signals needed to be driven by the client and the signals coming out of the hard MAC.

 

I already spy the client side signals (rx_ll_sof_n_0, rx_ll_eof_n_0_i, tx_ll_sof_n_0_i, tx_ll_data_0_i, ...) --> nothing 

What valid signals coming out of the hard MAC ?

 

 

Is it because the gtx_clk_0 clock comes directly from a DCM (xilinx warning)?

 

 To my knowledge: 

Yes. There is an app node that has this done. app node is xapp957 on the xilinx website.

Yes

 

 

Has anybody had similar problems?  Any solutions?

 

 To my knowledge:  

 I'm in the same boat :-)

 

 

 Let me know of your progress.

 

 

I am continuing my tests and I want you aware of my progress.

 

Thank you and good luck to you too.

 

Eric

 

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Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Eric,

 

 What type of packet are you sending? I noticed the MAC reject IEEE 802.3 frames (I may be wrong), but Etherent II frames work fine :-). I am doing more investigation :-)

 

Thank you,

Vince

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Visitor egueutier
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Registered: ‎04-09-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Vince,

 

The packets sent are IEE 802.3 type (specifiaction tolerated by Xilinx TEMAC).

At the level of your application, you noticed that the MAC is working properly for Ethernet II packets, but not for IEE 802.3 packets ??

I am continuing my researches also.

 

Thanks

Eric

 

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Registered: ‎03-23-2009

Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Hi all,

 

I have the example design working nicely ;-).

 

I have made changes to the top level code and it is attached to this post. Unfortunately, the MAc is always sending. The Mac is sending all 0x00s in the packet. I have followed the timing diagram and it works well in simulation.

 

Did anyone encounter this problem or have any suggestions.

 

Thank you,

Vince

P.S. I haven't finished my test on the packet type it is excepting.

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Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

I have attached the synthesis report of the core. In case it may help.

 

Does  anyone know what the following means?

 

WARNING:Xst:1540 - "d:/EMAC_TRI_MOD/pcores/emac_tri_mode_gmii_example_design_v1_00_a/hdl/vhdl/emac_tri_mode_gmii_example_design.vhd" line 664: Different binding for component: <fsl_v20>. Ports <FSL_M_Data,FSL_S_Data> do not match.

 

Thank you,

Vince

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Visitor girardeyr
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Re: ML506 Ethernet MAC: cannot get example design to work with ISE.

Hi Vince,

 

I had the same warning (Xst:1540). It means that the port declaration in the entity and the component are different (to and downto)

 

As an example:

entity Test is
 port (
  Data     : out std_logic_vector(0 to 15)

  );
end Test;

 

....

 

entity Top is

....

end Top;

architecture Behavioral of Top is

      component Test is

             port (

                     Data      : out std_logic_vector(15 downto 0)

                     );

      end  component;

.... 

 

Best Regards

Romuald

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