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Visitor teastlake313
Registered: ‎05-28-2019

Pmod SD on BASYS3 in Vivado 2018.3


Working with a Digilent Pmod SD on their BASYS 3 (Artix 7). I've managed to work out the HW so there are no critical warnings. Looks like this:20190528_Uart04_Block.PNG

The SDK part is a C++ example from Digilent board library:

/* Revision History:                                                          */
/*                                                                            */
/*    08/10/2016(TommyK):   Created                                           */
/*    01/20/2018(atangzwj): Validated for Vivado 2017.4                       */
/*                                                                            */

#include "PmodSD.h"
#include "xil_cache.h"
#include "xil_printf.h"

void DemoInitialize();
void DemoRun();

int main(void) {

   return 0;

void DemoInitialize() {


void DemoRun() {
   DFILE file;

   // The drive to mount the SD volume to.
   // Options are: "0:", "1:", "2:", "3:", "4:"
   static const char szDriveNbr[] = "0:";

   FRESULT fr;
   u32 bytesWritten = 0;
   u32 bytesRead, totalBytesRead;
   u8 buff[12], *buffptr;

   xil_printf("PmodSD Demo Launched\r\n");
   // Mount the disk
   DFATFS::fsmount(disk, szDriveNbr, 1);

   xil_printf("Disk mounted\r\n");

   fr = file.fsopen("newfile.txt", FA_WRITE | FA_CREATE_ALWAYS);
   if (fr == FR_OK) {
      xil_printf("Opened newfile.txt\r\n");
      fr = file.fswrite("It works!!!", 12, &bytesWritten);
      if (fr == FR_OK)
         xil_printf("Write successful\r\n");
         xil_printf("Write failed\r\n");
      fr = file.fsclose();
      if (fr == FR_OK)
         xil_printf("File close successful\r\n");
         xil_printf("File close failed\r\n");
   } else {
      xil_printf("Failed to open file to write to\r\n");

   fr = file.fsopen("newfile.txt", FA_READ);
   if (fr == FR_OK) {
      buffptr = buff;
      totalBytesRead = 0;
      do {
         fr = file.fsread(buffptr, 1, &bytesRead);
         totalBytesRead += bytesRead;
      } while (totalBytesRead < 12 && fr == FR_OK);

      if (fr == FR_OK) {
         xil_printf("Read successful:");
         buff[totalBytesRead] = 0;
         xil_printf("'%s'\r\n", buff);
      } else {
         xil_printf("Read failed\r\n");
   } else {
      xil_printf("Failed to open file to read from\r\n");

   while (1);

I'm able to compile and load this to the DUT with no errrors, but there is no activity on the SD card pins (checked with DSO) and nothing gets written to the SD card. Looking into the SDK Debugger, the code is running but not sure at what part of the C++ code (this due to a disconnect with the ASM vs the high-level code). It just appears to loop doing a whole lotta nuthin.

I'm suspecting the possibility of version incompatibilities (2017.4 vs 2018.3). I did get some [IP_Flow 19-4965] errors saying the board value was defined as "arty" instead of basys3, but wisdom on the boards suggested this was OK to click through. Also, I didn't find anything related to this that could be corrected.

So my HW config looks like other pictures I've seen. I did have to switch to JC to eliminate some other HW conflict warnings. So I hope to get some troubleshooting hints here.

I've also considered that using 100 MHz Output Clk might be too fast for the SPI or the SD, but if that was the case I'd have at least seen some activity on the SD pins.

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3 Replies
Visitor teastlake313
Registered: ‎05-28-2019

Re: Pmod SD on BASYS3 in Vivado 2018.3


Adding more info... The PmodSD.h file points to DXPISDVOL.h:20190529_03_Syntax03.PNG

Now I see that the DXPISDVOL.h file contains a syntax error:

First part of DXPISDVOL.h:


Second part of DXPISDVOL.h:


I admit to not being a World class C++ programmer, but AFAICT the class definition is not right. But when I try to rearrange it, the compiler resets it to the original code shown above. Strange thing is that the compiler warnings don't mention this syntax error.

Would be grateful for any advice here.

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Visitor teastlake313
Registered: ‎05-28-2019

Re: Pmod SD on BASYS3 in Vivado 2018.3

Here is the Vivado 2018.3 project file:

Link to the Vivado 2018.3 project file

This project was created using guidance from Digilant guide for Pmod IP's and Vivado IP Integrator . I had to selectively piece the examples together, and there was also a rqmt for this file Digilent 2018.2 library support .

I would hope going from 2018.2 to 2018.3 would not be a project-killer. Hoping to stay with the latest Vivado 2018.3 installed, and get some advice on how to fix what I've built so far.

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Visitor teastlake313
Registered: ‎05-28-2019

Re: Pmod SD on BASYS3 in Vivado 2018.3

Looking at this here link, there is Basys-3-Master.xdc.

Scrolling down to Line 180 has this mapping for JC:

##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]

Near the bottom of their Reference Manual shows the mapping for Pmod JC:

Screenshot from 2019-05-30 20-09-03.png

So what's bugging me is the HW mapping is non-contuguous, but they're trying to create a contiguous format in the Basys-3-Master.xdc file. From my experimentation, this does not work. I was, however, able to get continuity to the Pmod JC pins when I changed the [get_ports {JC[n]}] to match the HW mapping numbers in the manual. This effort was done using very simple Verilog code and mapping the Basys3 switches to the JC header. Full control was then achieved.

So I ask for advice on if this makes a difference when designing by a block diagram. AFAICT, this PmodSD board has accurate HW documentation, but some of the SW support files were copied from the Arty board and not remapped to Basys 3.

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