UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor nvenugop
Visitor
108 Views
Registered: ‎02-05-2019

RFSoC - ZCU111 - Data Convertor - Vivado Simulation

Greetings.

I am trying to simulate RFSOC data convertor block. So far in Vivado example project implementation, I am able to run the ADC and DAC examples seperately. However, I am not able to figure out, how to change the input signal properties to the ADC and DAC. For instance, I am finding it difficult to feed a Sine wave to the DAC and viceversa to ADC.

Also, is there a way to simulatenously simulate both ADC and DAC in same design and Pipe the output of one to other?

Thanks in advance!

Nanda

0 Kudos
1 Reply
Community Manager
Community Manager
43 Views
Registered: ‎08-30-2011

回复: RFSoC - ZCU111 - Data Convertor - Vivado Simulation

Hi,

There are blocks in example design named "ADC source" and "DAC sink" for the customer to feed stimulus to ADC and DAC.

The register map of these two blocks are introuduced in PG269 section"RF-ADC Data Capture Block" and "RF-DAC Data Stimulus Block".

Take DAC as an example. It needs the user feed the data to the particular register address and then enable the channel before sending the data to the DAC.

Thanks,

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------