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Observer sapril1229
Observer
9,092 Views
Registered: ‎02-02-2014

Re-using the K7 Connectivity TRD in a "real" design"

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I've been handed a PCB with a xc7k325tffg900-2.  It's been functionally verified so now it's time to implement a custom design that has major functional pieces comprised of a SG DMA engine, 10GE, and PCIe interface that are identical to the K7 Connectivity TRD (UG927 v5.0.1) as well as the FPGA itself.   I have rebuilt the TRD using Vivado 2013.4 on the KC705 eval platform and successfully ran the demo using the supplied software. 

 

Back to my custom board:  I have started by creating a pin planning project and assigned all the I/Os, as well as the proper I/O standards, signal directions, etc,  At this point I would like to know if it's considered practical to take the TRD and repurpose it for a custom board using the "Designing with the TRD platform" guide from chapter 5 of UG927.  Does anyone have any experience doing this, or can anyone provide some advice (e.g. proper steps to take) in this area?  My goal is to get something up and running as fast as possible.  for example, as a first step in the process should I export the pinout (csv) from the TRD and compare it with the custom pinout (csv)?   ...or should I try loading my pin planning project and just read in the sources from the TRD, and fix the pinout later?  

 

Thanks!

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Scholar kotir
Scholar
15,307 Views
Registered: ‎02-03-2010

Re: Re-using the K7 Connectivity TRD in a "real" design"

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Hi ,

 

Yes , i believe you should not see any problems to port the TRD on custom board if below things are taken care.

 

 

1. PCIe Pinouts and clock constraints for custm board

2. MIG core might required to be regenerated for your board.

3. pinouts fot 10Gphy blocks.

 

Over all design timing closure for custom board pinouts.

 

Regards,

KR

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Scholar kotir
Scholar
15,308 Views
Registered: ‎02-03-2010

Re: Re-using the K7 Connectivity TRD in a "real" design"

Jump to solution

Hi ,

 

Yes , i believe you should not see any problems to port the TRD on custom board if below things are taken care.

 

 

1. PCIe Pinouts and clock constraints for custm board

2. MIG core might required to be regenerated for your board.

3. pinouts fot 10Gphy blocks.

 

Over all design timing closure for custom board pinouts.

 

Regards,

KR

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Observer sapril1229
Observer
9,062 Views
Registered: ‎02-02-2014

Re: Re-using the K7 Connectivity TRD in a "real" design"

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Thanks - my strategy so far has been:


1.  IO Planning on the custom design.

2.  Export IO from TRD

3.  Merge the two via spreadsheet and then translate re-assigned pins to TRD which will eventually turn the TRD into the custom design (pin-wise anyway).  This is proving to be be very time consuming.  The devil is in the dtails as they say.  My goal, of course, is to make as few modifocations as possible to the TRD so I can build (or tear down) upon a working baseline.  The reality is that I am making small changes, re-synth, and re-implement each time.  I will get to a point where it will be time to create a bit file and slam it in.

 

I will keep you informed as I progress through this. 

 

 

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Visitor sapril
Visitor
8,490 Views
Registered: ‎04-28-2014

Re: Re-using the K7 Connectivity TRD in a "real" design"

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The biggest problem I am having at this point is trying to reproduce the old XPS-generated axilite_interconnect so that I may expand it;s ports. There doesn't seem to be any Vivado IP that is a direct match.
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