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Explorer
Explorer
4,746 Views
Registered: ‎03-25-2010

SMA and GTP_DUAL in ML507

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Hello,

 

I want to use the MGT X0Y4 connected to the pins SMA_TX and SMA_RX.

 

However I can see that the SMA is connected to the Transceiver #1 of the GTP_DUAL.

 

And for some protocols like PCIe According with the UG341 "Each GTP_DUAL tile contains two transceivers. The even numbered lane is always placed on transceiver 0 and the odd numbered lane is on transceiver 1 for a given GTP_DUAL in use.", so I can not connect the SMA pins to the LANE0 of PCIe.

 

The question is what kind of communication (high speed serial) can I implement that supports the SMA connection schema?.

 

I guess PCIe is not possible.

 

 

Thanks

 

REGARDS,

 

DABG

lane0.JPG
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1 Solution

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Explorer
Explorer
6,174 Views
Registered: ‎03-25-2010

Re: SMA and GTP_DUAL in ML507

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Thanks to I have solved my issue. The system is correctly placed & routed.

 

You can find the solution in this post:

 

http://forums.xilinx.com/t5/PCI-Express/Lane-numbers-and-GTP-transceivers-Locations/m-p/151544#M2569

 

The simple answer was you have to swap the GTPs in the wrapper pcie_gt_wrapper.v

 

Now I need to do the same but with the wrapper of the PLB2PCIe bridge.

pcie_v5_par_ok.JPG
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5 Replies
Xilinx Employee
Xilinx Employee
4,743 Views
Registered: ‎01-03-2008

Re: SMA and GTP_DUAL in ML507

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MGT pins are dedicated pins.  Some of the MGTs are connected to the PCIe fingers on the board and some of them are connected to other components like the SMAs and SFP.

 

The table that you attached is inconsistent.  The cell that you circled should have been blank instead of N/C or all of the other blank cells should have had an entry of N/C.

------Have you tried typing your question into Google? If not you should before posting.
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Explorer
Explorer
4,740 Views
Registered: ‎03-25-2010

Re: SMA and GTP_DUAL in ML507

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Hello mcgeet,

 

I took the table from the document ug341 page 111.

 

http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

 

The problem is that in the kit ML507 the SMA_TX and SMA_RX are phisically connected to the Transceiver 1. So I have not been able to test a x1 lane configuration.

 

 

Thank you in advance for your reponse.

 

Kind regards,

 

DABG.

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Xilinx Employee
Xilinx Employee
4,736 Views
Registered: ‎01-03-2008

Re: SMA and GTP_DUAL in ML507

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> The problem is that in the kit ML507 the SMA_TX and SMA_RX are physically connected to the Transceiver 1

 

Each GTP_DUAL has side 0 and a side 1.

 

The GTP_DUAL in Bank 116 is connected to the SFP (0) and SMA (1) on the ML507.

The GTP_DUAL in Bank 118 is connected to the PCIe (0) and pcb loopback (1) on the ML507.

------Have you tried typing your question into Google? If not you should before posting.
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Explorer
Explorer
4,729 Views
Registered: ‎03-25-2010

Re: SMA and GTP_DUAL in ML507

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Hello,

 

I do not have SFP cables, so I need to use just the SMA. (In my project I have to communicate two kits :ML507 and ML605).

 

For example with PCIexpress (x1 lane) generated with LOGICORE:

+if I use the SIDE 0, everything is OK,

+but if I use just the SIDE 1 is impossible to route the design.

 

The  question is: Can I Use just the SIDE 1 of the GTP_DUAL?

 

Thank you very much,

 

Kind regards,

 

DABG

 

fpga_editor.JPG
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Explorer
Explorer
6,175 Views
Registered: ‎03-25-2010

Re: SMA and GTP_DUAL in ML507

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Thanks to I have solved my issue. The system is correctly placed & routed.

 

You can find the solution in this post:

 

http://forums.xilinx.com/t5/PCI-Express/Lane-numbers-and-GTP-transceivers-Locations/m-p/151544#M2569

 

The simple answer was you have to swap the GTPs in the wrapper pcie_gt_wrapper.v

 

Now I need to do the same but with the wrapper of the PLB2PCIe bridge.

pcie_v5_par_ok.JPG
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