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Newbie danstroem
Registered: ‎07-27-2011

Spartan-3e DDR controller out-of-the-box

This relates to the Digilent Starter Kit: http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD


I'm a newbie and had some headaches getting the DDR SDRAM core to work. The onboard 50MHz crystal is used for simplicity. The documentation did mention a DCM, which generates the clock signal for the DDR component, but it did NOT mention, that you have to manually add a second DCM, to generate the 133MHz clock. Additionally the example designs of ISE 9.2 and 11.5 have many timing violations for the DDR signals, so I decided to start the newest Memory Interface Generator (MIG 3.61 from ISE 13.2) to create a new design.


Digilent violated the design needed by MIG on the PCB, so some hand edits were needed, which are also mentioned in the folder_details.txt of the reference design in 9.2 and 11.5. So if anyone is looking for an out-of-the-box solution to get the DDR to work, like me, it's attached. For my project the DDR should just work and not be a project of its own. I can't give any support for the attached design.


There are some timing violations regarding the clock, I suppose because of the low quality clock of the dcm. But it works reliably on the board and other signal are ok. Another drawback is, that the data mask is disabled and can not be used, because rst_dqs_div signal uses one of the pins.


Relating to: http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-3E-DDR-MIG/m-p/32967

2 Replies
Newbie maquicoser
Registered: ‎04-01-2012

Re: Spartan-3e DDR controller out-of-the-box

Interesting post. I view the other user response.


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Registered: ‎11-21-2014

Re: Spartan-3e DDR controller out-of-the-box

Hey there!


Did this actually work on the S3-eSK hardware?. I can see you don't use the DDR clock feedback signal (B9 on the S3-eSK) to the clock signal against the DDR pin or the Delay Normalization Loop. Any idea how this is overcome?





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