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Registered: ‎11-05-2018

U-Boot or ATF seems to disable IPI for the A53 (ZCU102)

Hi,

As part of a built-in test, I have a baremetal app that runs on the A53-1 after the FSBL that communicates with A53-2, A53-3, R5-0, and R5-1 through IPI. When I load this (through QSPI or on the System Debugger), everything is hunky-dory: the app is able to communicate with the other cores (actually A53-3 for some reason is not working, but I think that may be an unrelated problem). 

When I put U-Boot and ATF in my .bif file, on A53-0, IPI seems to not work amongst the A53 cores. I can't communicate from my A53-1 app to the other cores. However, IPI from A53-1 to either of the R5 cores does work. 

So what I thought is that U-Boot disables IPI for the whole processor when it boots up because U-Boot doesn't use interrupts. But, I have also noticed, that if I include ATF and exclude U-Boot, it is still the case that IPI works for the R5 but not the A53. 

Any idea what's going on? 


Here is my .bif file:

 

the_ROM_image:{
		[bootloader, destination_cpu=a53-0] detailed_fsbl.elf
		[pmufw_image]pmufw.elf

		// U-Boot
		[destination_cpu = a53-0, exception_level=el-3, trustzone]bl31.elf
		[destination_cpu = a53-0, exception_level=el-2]u-boot.elf

		// Built-in test - communicates via IPI with the other four cores
		[destination_cpu = a53-1]builtintest.elf

// These just respond to the leader [destination_cpu = a53-2]echo_a53_2.elf [destination_cpu = a53-3]echo_a53_3.elf [destination_cpu = r5-0]echo_r5_0.elf [destination_cpu = r5-1]echo_r5_1.elf }

 

My sending code:

 

static void wakeup_core(CoreId id)
{
	// Initialize
	XIpiPsu ipi_instance;
	XIpiPsu_Config *config_ptr = XIpiPsu_LookupConfig(0);
	if(config_ptr == NULL)
		bit_fail("config_ptr == NULL");
	if(XIpiPsu_CfgInitialize(&ipi_instance, config_ptr, config_ptr->BaseAddress))
		bit_fail("XIpiPsu_CfgInitialize failed");

	// Select core to send interrupt to
	if(XIpiPsu_TriggerIpi(&ipi_instance,
			id==R5_0?
				XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK:
			id==R5_1?
				XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK:
			id==A53_1?
				XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK:
			id==A53_2?
				XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK:
			id==A53_3?
				XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK:
			// Otherwise...
				(printf("[warning goes here]\r\n"), 0)
			))
		bit_fail("[fail information goes here]");
}

My setup code for the receiver:

 

 

        static XIpiPsu_Config* ipi_config_ptr;
	static XScuGic_Config* gic_config_ptr;
	static XIpiPsu ipi_instance;
	static XScuGic gic_instance;


	Xil_DCacheDisable();

	// Look up config data
	ipi_config_ptr = XIpiPsu_LookupConfig(XPAR_XIPIPSU_0_DEVICE_ID);
	if(ipi_config_ptr==NULL) return FAIL;
	// Init with config data
	if (XST_SUCCESS != XIpiPsu_CfgInitialize(&ipi_instance, ipi_config_ptr, ipi_config_ptr->BaseAddress))
		return FAIL;

	// SETUP GIC
	gic_config_ptr = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);
	if(gic_config_ptr==NULL) return FAIL;
	if(XST_SUCCESS != XScuGic_CfgInitialize(&gic_instance, gic_config_ptr, gic_config_ptr->CpuBaseAddress))return FAIL;

	if(XST_SUCCESS != XScuGic_SelfTest(&gic_instance))
	{
		return FAIL;
	}

	//Connect handler
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &gic_instance);
	if(XST_SUCCESS != XScuGic_Connect(&gic_instance, (ipi_instance.Config.IntId), (Xil_InterruptHandler) handler, (void*) &ipi_instance))
		return FAIL;
	XScuGic_Enable(&gic_instance, ipi_instance.Config.IntId);
	Xil_ExceptionEnable();


	// Enable reception of IPIs from all CPUs
	XIpiPsu_InterruptEnable(&ipi_instance, XIPIPSU_ALL_MASK);
	// Clear any existing interrupts
	XIpiPsu_ClearInterruptStatus(&ipi_instance, XIPIPSU_ALL_MASK);

	Xil_DCacheEnable();
return PASS;

After setting up, the receiver just waits with the WFI instruction

 

My ultimate goal is to have U-Boot on A53-0 communicate with the app on A53-1, which then communicates with the rest of the cores as a way of proving that each of the cores work.

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