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Observer ajroth
Observer
8,377 Views
Registered: ‎04-14-2015

VC707 GTX QUAD113 SFP use Si5324, SGMII use SGMII _CLK - UG476 single external ref clk confusion

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VC707 - Vivado ~2014.2 tools (trying 2015.1 or 2 evantually as well..)

 

What is the best way to generate cores to have both the VC707 GTX SFP use Si5324 and SGMII use SGMII _CLK since both are in QUAD113.  The Si5324 clk is from MGTREFCLK0 QUAD114 while the SGMII_CLK is from MGTREFCLK0 QUAD113.

 

I have the SGMII ethernet / PCS/PMA working via AR59968 TEMAC PSCPMA -

1- However I generated the "core with shared logic" for the pcs/pma core for SGMII, do I need to go back and change this?

 

Now for the Si5324 clk coming in which I know is good seen via a probe I have the following questions:

2- Should I configure the signal from the Si5324 to be "Low swing LVDS", LVDS, or LVPECL?  I'm guessing Low swing LVDS should be good after looking at things.

3- I've generated the core without shared logic - and instantiate the IBUFDS_GTE2 and tried tying this to both gt0_gtrefclk0_in/1, and the gtsouthrefclk0/1 in.  It doesn't appear to map to gtrefclk0 or 1 when I tie it to those when viewing the routed design in device view...

 

I've noticed documentation UG476:

"Figure 2-6 shows a single external reference clock with multiple transceivers in multiple
Quads. The user design connects the IBUFDS_GTE2 output (O) to the GTREFCLK0 ports
of the GTXE2_COMMON and GTXE2_CHANNEL primitives for the GTX transceiver, and
GTHE2_COMMON and GTHE2_CHANNEL primitives for the GTH transceiver. In this
case, the Xilinx implementation tools make the necessary adjustments to the north/south
routing as well as pin swapping necessary to route the reference clocks from one Quad to
another when required."

 

4- Do I need to instantiate GTXE_COMMON as well even though I don't want/need the QPLL clk I just want to use the CPLL clk?

5- Is tieing the IBUFDS_GTE2 output to only gt0_gtgrefclk0_in the correct path, and all the others tie to gnd?

6- Will there not be a conflict with the SGMII_CLK which the SGMII using from gtefclk0_in? - do I need to modify anything on my working PCS/PMA core? (source files are encrypted for the GTX gtwizard for the pcs/pma SGMII core?! so I can't see what it was set up as...)

 

Thanks - this works in simulation, but I can't get CPLL lock.  You may reference further background at http://forums.xilinx.com/t5/Connectivity/GTX-transceiver-wizard-set-CPLLREFCLK-quot-101-quot-in-property/m-p/643571#M8223 which was a different beginning question to figure out how to get clks here (feed si570 to si5324)

 

 

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Observer ajroth
Observer
16,045 Views
Registered: ‎04-14-2015

Re: VC707 GTX QUAD113 SFP use Si5324, SGMII use SGMII _CLK - UG476 single external ref clk confusion

Jump to solution

Solved -

 

Answers/hints for future viewers:

 

1- no

2- Low swing LVDS working

3- Geberate without advanced clk - tie only gtrefclk0 to output of IBUFDS_GTE2 and tools map it automatically as needed to SOUTHREFCLK you can see in device viewer,  but you don't need to tough CPLLREFSEL's or SOUTHREFCLK signals..

 

4- no

5- yes, just tie the GTREFCLK0

6- ok

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Observer ajroth
Observer
16,046 Views
Registered: ‎04-14-2015

Re: VC707 GTX QUAD113 SFP use Si5324, SGMII use SGMII _CLK - UG476 single external ref clk confusion

Jump to solution

Solved -

 

Answers/hints for future viewers:

 

1- no

2- Low swing LVDS working

3- Geberate without advanced clk - tie only gtrefclk0 to output of IBUFDS_GTE2 and tools map it automatically as needed to SOUTHREFCLK you can see in device viewer,  but you don't need to tough CPLLREFSEL's or SOUTHREFCLK signals..

 

4- no

5- yes, just tie the GTREFCLK0

6- ok

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