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Observer grzegorzkorcyl
Observer
358 Views
Registered: ‎04-27-2018

VCU108 and USER_SMA_CLOCK

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I am unable to drive a clock out through these two SMA connectors (AR14 and AT14)

Did anyone manage to use the USER_SMA_CLOCK IO on VCU108 board?

 

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Xilinx Employee
Xilinx Employee
283 Views
Registered: ‎06-13-2018

Re: VCU108 and USER_SMA_CLOCK

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Hello @grzegorzkorcyl,

Thank you for sharing the information.

I assume and believe that you are trying to route the system clock on SMA connector. Can you please confirm that are you following the User_Clock => IBUFGS=> IBUFG => ODDR => OBUFDS => SMA connector flow to route the System clock? If no, you need to connect the buffers in between the user clock and the SMA connector. At my end, I have tested and I am getting the clock at SMA connector.

Regards,

Naveen

 

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Moderator
Moderator
313 Views
Registered: ‎04-12-2017

Re: VCU108 and USER_SMA_CLOCK

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Hello @grzegorzkorcyl 

what failure you are observing and what is the clock output do you see?

Are you running any example design based on VCU118?

Please share with us more details.

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Observer grzegorzkorcyl
Observer
291 Views
Registered: ‎04-27-2018

Re: VCU108 and USER_SMA_CLOCK

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Dear kvasantr,

I have tried it with a minimal design using two boards connected with provided SMA cables:

- on the first one I route the system clock out to the SMA connectors (raw signal, without ODDR, just OBUFDS)

- on the second one, I receive the signal and route to an LED, one raw to check with a scope and another one that drives the counter.

Basically I have nothing on the output SMA connectors on the first board (checked with a scope) and I see nothing on the receiving board, so I susspect that the pinout or schematics might be wrong.

Please note it is the VCU108 platform not VCU118. Do you know any designs that use these connectors?

 

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Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎06-13-2018

Re: VCU108 and USER_SMA_CLOCK

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Hello @grzegorzkorcyl,

Thank you for sharing the information.

I assume and believe that you are trying to route the system clock on SMA connector. Can you please confirm that are you following the User_Clock => IBUFGS=> IBUFG => ODDR => OBUFDS => SMA connector flow to route the System clock? If no, you need to connect the buffers in between the user clock and the SMA connector. At my end, I have tested and I am getting the clock at SMA connector.

Regards,

Naveen

 

Observer grzegorzkorcyl
Observer
277 Views
Registered: ‎04-27-2018

Re: VCU108 and USER_SMA_CLOCK

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Thanks a lot Naveen for confirmation that it works on your side.

I have managed to get another VCU108 unit and it works there, seems like there is a problem with connectors on my board...

 

 

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Observer grzegorzkorcyl
Observer
251 Views
Registered: ‎04-27-2018

Re: VCU108 and USER_SMA_CLOCK

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Just for future reference, I have the "real" reason why I had problems driving the USER_SMA_CLOCK pins:

On one of the VCU108 boards I had a FMC board connected. When booting up, the system controller on VCU read the EEPROM from the mezzanine and then sets the VADJ accordingly. The EEPROM on my FMC board was empty and so the VADJ was being set to 0. Without the mezzanine it starts with 1.8V. Turns out the USER_SMA_CLOCK pins are located in the same FPGA bank that FMC_HPC0_LA* pins and is powered by the VADJ voltage. 

That's why reading an empty EEPROM from the FMC card was powering down the bank that drives USER_SMA_CLOCK pins.

Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎06-21-2018

Re: VCU108 and USER_SMA_CLOCK

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Thanks for the explanation, it will help someone in the future!

Cheers,
Andres

 

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Moderator
Moderator
224 Views
Registered: ‎04-12-2017

Re: VCU108 and USER_SMA_CLOCK

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Hello @grzegorzkorcyl 

Really glad for sharing that information.

Yes, our EVB's adhere to VITA standard for FMC HPC and LPC connectors and the behavior you observed with VADJ is absolutely correct.

we have clearly mentioned this on page number 96 of UG1066 of VCU108

vadj.PNG

thank you  

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