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Visitor sandkumc663
Visitor
180 Views
Registered: ‎07-15-2019

VCU118 design using 300 sys clock for generating processor clock

Hi

I tried creating a microblaze design for vcu118 board using sys clock 300M driving clocking wizard for generating 100M which is used for processor and peripheral clock.

However design did not work. I did not see hello world message on UART. 

I even tried using sys clock 125 and fixed clock 250M but unsuccessful.

Only design which is working for me is using DDR4 MMCM generating 100MHz for processor sub system. Input to DDR4 was 250MHz clock.

Can xilinx comment?  Can xilinx provide simple design example of uBlaze + uart + gpio + clock wizard input 300M and output 100M working for vcu118 board?

Thanks

 

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4 Replies
Explorer
Explorer
168 Views
Registered: ‎10-12-2018

Re: VCU118 design using 300 sys clock for generating processor clock

Hi @sandkumc663 

Is your (non working) design critical warning free?

  • If no: Please fix those HW issues
  • If yes: Be sure, that your program is running. Can you blink LEDs from software? (Please conect LEDs on an AXI-GPIO module.) 
    • If yes: There should be something with the UART itself.
    • In no: Can you blink LEDs from TCL command? (Open an XSCT console, and enter: mwr <gpio_baseaddress> <LED_data>)
      • If yes: Your clock should be OK. There should be something with the launch of the program.
      • If no: Check the clock itself. Connect a chipshope to monitor the problematic clocks. (The chip-scope core should use the working clock.)
        Open the schematic. Be sure that problematic clocks connected to proper input pin/pad. A proper buffer is located on them.

Can xilinx provide simple design example...? This is a free community forum. I believe nobody has time/enthusiast for that...

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Visitor sandkumc663
Visitor
152 Views
Registered: ‎07-15-2019

Re: VCU118 design using 300 sys clock for generating processor clock

Thanks for reply.

As i mentioned using DDR4 generated processor clock worked without any trouble, I was expecting a simple design without ddr4 to work without any issue.

Attached is block diagram using 125Mhz as input to clocking wizard for generating processor 100 mhz clock.

Let me know if anything is wrong with it.

I hope xilinx folks can share quickly anything wrong in design from their experience. Almost all of xilinx examples uses DDR4 output 100Mhz clock for processor clock. Any reason for that?

ublaze_125m_uart.PNG
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Explorer
Explorer
128 Views
Registered: ‎10-12-2018

Re: VCU118 design using 300 sys clock for generating processor clock

Please answer all of these question to give more help:

Is your non-working design critical warning free? (Run the complete compiling and see error and critical-warning messages)
NO: Please fix those HW issues
YES: Be sure, that your program is running.

Are you sure that the program is running on non-working design? Can you blink LEDs from software? (Try to toggle some leds connected to led_8bits IP.)
YES: There should be something with the UART itself.
NO: Can you blink LEDs from TCL command? (Open an XSCT console, and enter: mwr <gpio_baseaddress> <LED_data>)

Can you blink LEDs from TCL command on non-working design?
YES
: Your clock should be OK. There should be something with the launch of the program.
NO:
Check the clock itself.

Clock check:

Toggle a simple register from the native 125MHz clock and the generated 100MHz. Connect a chipshope to that register. (The chip-scope core should use the working 300MHz clock.)
Open the schematic. Be sure that problematic clocks connected to proper input pin/pad. A proper buffer is located on them.
Check the settings of the clock wizzard. Have you updated the input clock frequency to 125MHz?
Check the constraint of the 125MHz clock. Open the Implemented design, and report clocks.

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Visitor sandkumc663
Visitor
58 Views
Registered: ‎07-15-2019

Re: VCU118 design using 300 sys clock for generating processor clock

Hi

I went through reports and did not find any critical warnings. Timing report see no violation and clock report as expected.

Attach is clock path report. Looks ok.

Timing reports shows clock frequency input 125M and output 100M.

I think I will try BIST provided with kit and see that clock test for 125/300M for my vcu118 board is passing or not.

Thanks

ublaze_125m_uart_clk_rpt.PNG
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