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Registered: ‎03-15-2018

Vivado 2017.4 crashes running examples for Xilinx ZCU102 evaulation board

Hello,

I am new to using the Vivado tools, and probably doing something by accident which is causing a cascaded series of problems.This email has several sections: System Description, History, and Questions

System

First, I installed the licensed tools on a Dell Precision 7520 configured as follows:

CPU:   Xeon CPU E3-1535 v6 clocked at 3.10 GHx

           This is a Quad Core device

Dram:  32 Gbytes

System type:  64 bit operating system, x64-based processor

OS:      Windows 10 Pro for Workstations

Version: 1709

Build:    16299.309

 

Second: the specific of evaluation kit I am using is the Zynq Ultrascale+ MPSoC ZXU102 Evaluation Kit.

 

History:

I receieved my ZCU 102 2 weeks ago, and the Dell computer a few days later.

I am going to recount my steps, because I am not sure which steps/problems are linked to what:

The ZCU BIST exercise was passed quickly, but I did not have the UART interface setup, nor Tera Terminal running, in part because I did not the Dell at that time.

When the Dell arrived, I did not download the device drivers for the Silicon Labs CP2108 device.

I ran both Vivado and Vivado HLS through several example projects.

I powered up the ZCU 102 evaluation board and ran the BIST, initially all relevant lights came up green.

At this point, I may have messed things up. I was a bit confused about the setting for SW4. These may be part of the problem.

I ran Vivado with the example of the Zynq Ultrascale with DRAM targeting the ZCU 102. It generated a bit stream. When I turned on Hardware Manager I ran autoconnect to find the ZCU 192 board, which it did.

However, the pattern did not program.

My thought was to return to the initial BIST, this time with Tera Terminal on.

This is when I realized that the Silicon labs part did not have its device driver loaded, which I then did.

There are four com ports listed associated with the Silicon Labs part. I tried powering down the ZCU 102 and rerunning Tera Terminal with the various settings. Hardware Manager was still running.

At this point, Vivado terminated unexpectedly for the first time.

I turned off the card, and reset the Windows computer.

The second time I ran Vivado, got to the Hardware Manager, started the board, Vivado and the Hardware Manager quickly terminated.

Since then, I tried making new projects based upon the same example project and upon the simpler Zynq+Ultrascale project. The simpler project had previously made a bit stream, but I had not run the hardware manager. Both of these runs lead to unexpected terminations before generating bit streams. I believe the crashes were in synthesis.

I also made experimental runs with Vivado HLS, which also crashed and could not open previously generated projects.

At this point, I decided that my project folder may have been corrupted, so I renamed it to take it out of the Xilinx tools search path and made a new empty folder with the same name for Vivado projects and a separate folder for Vivado Hls projects. I tried several projects in each.

    The Vivado projects were based upon example projects, and each failed to complete synthesis. Vivado terminated unexpectedly on several occasions.

    The Vivado HLS projects, also based upon examples, failed to create their directory structure correctly, being unable to instantiate the source files.

Questions:

  1. Tera Terminal is now crashing unexpectedly. What should I do about this?
  2. Is there any way to scrub the existing tool set and start over without uninstalling the tools?
  3. Should I uninstall the Vivado tool set and reinstall it?
  4. I have the SW4 switch setting under control now, but how do I determine if the boot memory is corrupted?

Thanks,

Earle Jennings

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2 Replies
Scholar jmcclusk
Scholar
517 Views
Registered: ‎02-24-2014

Re: Vivado 2017.4 crashes running examples for Xilinx ZCU102 evaulation board

Run a memory test with the BIOS on your computer, first thing.  Be absolutely sure your PC isn't having memory problems.

 

Regarding hardware manager, it's true that you should never power off the FPGA board while the JTAG connection in hardware manager is running, since that can cause a crash or a hang of the JTAG driver,   but with the multiple crashes you are seeing, especially in synthesis?  and Teraterm too?   There are too many crashes to wave away as "just software".    It smells like a hardware issue with your new Dell.   Run the Dell through a set of diagnostics to be sure the PC hardware is solid. 

 

you may have to re-install Vivado,  There's a small possibility the install files are corrupted (unlikely).   If you do,  you should install it while using administrator privileges.  (right click on the installation file and select "run as admin").   

Don't forget to close a thread when possible by accepting a post as a solution.
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460 Views
Registered: ‎03-15-2018

Re: Vivado 2017.4 crashes running examples for Xilinx ZCU102 evaulation board

First, let me thank you for your help. I have worked with Dell and confirmed the DRAM of the host system is sound.

Next, I reinstalled the Vivado tools and confirmed two example projects, the Zynq + SOC and Zynq + Ultrascale examples were built similarly to the previous runs before things went haywire.

Then I closed Vivado and turned on Tera Terminal. I powered up the ZCU 102 board and got a surprise DS1 light was red indicating that the FPGA was hung up initializing. I did some looking around the Xilinx web site and found a program known as Xilinx BIT program for the ZCU 102, which I have downloaded and ran. Three of the tests failed

 

ZCU102 RTC

PING

IP Test

 

I believe that my quest should now be part of the hardware forum, in particular the ZCU 102 forum.

 

Thanks again,

Earle

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