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1,134 Views
Registered: ‎03-11-2019

ZCU102 Board User Interface test failed

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Hi all,
I ran the newest ZCU102 Board User Interface test and I ran into a few problems.
The ZCU102 RTC, IPI APP Test ,MIG PS DDR4 and PING failed for me.
Although I think they are working because they are failing for also my two other new ZCU102 boards. All of them failes at the UART step.

The red error message is the following :
"Could not connect to Serial Port. Is it being held up by another program?"

I don't use the ports while running the tests on other program and also the UART 01/02 TEST passed(?!).
To me it sounds like something is wrong with the GUI.
Maybe configuration problem.

I attached the log file to the post.
Thanks for everyone who is willing to help!

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
968 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

Thank you for sharing the requested information.

Due to an End of Life notification from Micron Technology, Inc. the DDR4 SODIMM part on the ZCU102 Evaluation Kit has changed. For more information please check AR-71961.

  • ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1.
  • ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.

You need to replace the FSBL source code file. Please check AR-72113. To work around this issue, you can replace the FSBL source code files with the attached .c/.h files in 72113-files.zip. this issue has been resolved in Vivado 2019.1

NOTE: This FSBL source file is only for Vivado 2018.3. Prior to Vivado 2018.3, customer needs to modify the DDR Configuration setting manually and then, they need to generate the FSBL source code File.

Please find the modified DDR configuration settings.

Capture.PNG

Hope this information will help you. Looking forward to hearing from you.

Regards,

Naveen

---------------------------------------------------------------------------------------------

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20 Replies
Xilinx Employee
Xilinx Employee
1,093 Views
Registered: ‎06-06-2018

Re: ZCU102 Board User Interface test failed

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Hi @dor_shmilovich ,

1.Are you facing this issue at time zero or after period of usage on all the 3 boards?

2.Please share the Board Power GOOD LEDS Snapshot and and also Board front side Snapshot at power ON. Better you provide me alll 3 Boards Snapshots.

3.Please go through this ZCU102 Debug Checklist and confirm me till step 4 you are fine for all 3 Boards?

4.Ensure that you have correctly followed XTP435 completely. Mainly Ethernet Setup and clock Setup. Please confirm me the same. 

5. For PING Test failing, you can refer this PING FAIL. For PS DDR4 depends on new SODIMM Part on Board.

6. Please confirm that there are no Tera Term window opened in your PC. 

7. To check the health of the board perform BIST TEST and share the results.

Note : If BIST Test fails, perform Flash Restoration(Download related files) and agin perform BIST Test and share the results.

Regards,

Deepak D N

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Xilinx Employee
Xilinx Employee
1,054 Views
Registered: ‎06-06-2018

Re: ZCU102 Board User Interface test failed

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Hi @dor_shmilovich ,

Any Update ?

Regards,

Deepak

Visitor sonadrin
Visitor
1,046 Views
Registered: ‎10-15-2018

Re: ZCU102 Board User Interface test failed

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Hi and thank you!

Update will come in a few days.

Couldn't work on it this week. 

988 Views
Registered: ‎03-11-2019

Re: ZCU102 Board User Interface test failed

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Hi again,
For now I do the steps that you wrote only on 1 board and then I will repeat the process with the other boards when I'll fix the first.
I tried your steps and I reached step 4 and stopped because it failed in the firmware update.
I will include the log of the zcu102_scui's log.

Should I continue with the steps anyway?
Also, here is my response per step by far :

1.I am facing the issue sometime after I start the tests in the xilinx interface test. most of the time (it is written in the log) when the test tries to use UART.
2.I will included the board power good leds. but I didn't understand which side is the front side that you were asking for. (is it the FMC connectors side?)
3.I can confirm that I ran through the ZCU102 Debug Checklist and its fine for this board.
4.This step failed when I tried to update firmware with the Xilinx BIT application.
6.I can confirm that there is not terra term window opened. If you want I can send you proof if you'll tell me what to do or picture.

Thanks for the help!

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Xilinx Employee
Xilinx Employee
969 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

Thank you for sharing the requested information.

Due to an End of Life notification from Micron Technology, Inc. the DDR4 SODIMM part on the ZCU102 Evaluation Kit has changed. For more information please check AR-71961.

  • ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1.
  • ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.

You need to replace the FSBL source code file. Please check AR-72113. To work around this issue, you can replace the FSBL source code files with the attached .c/.h files in 72113-files.zip. this issue has been resolved in Vivado 2019.1

NOTE: This FSBL source file is only for Vivado 2018.3. Prior to Vivado 2018.3, customer needs to modify the DDR Configuration setting manually and then, they need to generate the FSBL source code File.

Please find the modified DDR configuration settings.

Capture.PNG

Hope this information will help you. Looking forward to hearing from you.

Regards,

Naveen

---------------------------------------------------------------------------------------------

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----------------------------------------------------------------------------------------------

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Visitor sonadrin
Visitor
960 Views
Registered: ‎10-15-2018

Re: ZCU102 Board User Interface test failed

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So every tool from the xilinx site doesn't support the new ddr?

The interface test tool and the other tools are not valid for it?

Thank you again for the answers. 

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Xilinx Employee
Xilinx Employee
953 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

Thank you for your prompt response.

Your understanding is correct. This change has been done after the release of the Vivado 2018.3. If you are running the BIT test, I believe PS DDR test will fail. Please correct me if I am wrong. 

To check PS DDR I would like to suggest you please run the "Hello World" example design.

Regards,

Naveen

---------------------------------------------------------------------------------------------

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897 Views
Registered: ‎03-11-2019

Re: ZCU102 Board User Interface test failed

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Hi,
The PS DDR indeed fails in the interface test.
and also the hello world application doesn't work if I don't do the changes that you suggested above.
Can you please tell me when the new version of the interface test is released?
And if you can't tell, is there a way to be updated when it get released?

Thank you again and I will mark your answer as solution for now.

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Xilinx Employee
Xilinx Employee
880 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

Thank you for accepting my reply as an accepted solution. 

Can you please let me know which Vivado version you are using and which BIT test you ran?

In the latest XTP428  for BIT test, it has been mentioned that the provided example design will work for both SODIMMs. Did you run the latest BIT test?

xtp428.PNG

Regards,

Naveen 

 

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876 Views
Registered: ‎03-11-2019

Re: ZCU102 Board User Interface test failed

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I am using Vivado 2018.3.
Yes I ran the latest BIT test.
It still fails.

Thank you again.

Edit : You can check the log that I included in my first comment on this topic.

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Xilinx Employee
Xilinx Employee
829 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

I will check this issue internally and if necessary I will file a CR against the documentation. Thank you for bringing this issue to our attention.

Regards,

Naveen 

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Contributor
Contributor
545 Views
Registered: ‎02-14-2014

Re: ZCU102 Board User Interface test failed

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hello,

I have same issue and no one answered me ( in another topic)

my board is 0432055-05 and I replace the new fsbl from AR# 72113.

I use vivado 2018.3, but using vivado 2019.1 not help this issue.

Capture.PNG    this is DDR configuration:Capture.PNG

and this is boardUI.exe result:

Capture.PNG

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Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @dor_shmilovich,

I am checking this information with our Development Team. For that, I need the following details from you:

1.  Please share the specific SODIMM part number being used in the failing board.

2. Can you please check which DDR memory is there inside the SODIMM? Is it Micron or Kingston? Please open the cage and check this. 

3. Have you tried to run the lastest BIT test? If yes, is it failing? Please confirm.

Regards,

Naveen

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381 Views
Registered: ‎03-11-2019

Re: ZCU102 Board User Interface test failed

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Hi again @nmanitri,
sorry for the late response.
I didn't find a source how to open the cage so I don't know the part number of the SODIMM and the DDR inside it.
About the bit file though I can tell you that I downloaded the latest bit file and failed.

Thank you.

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Observer subu.rama
Observer
302 Views
Registered: ‎07-22-2018

Re: ZCU102 Board User Interface test failed

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I have the same issues. BIT to update firmware doesn't work. Board UI doesn't work. I have downgraded the UART drivers, ran both 2018.3 and 2019.4 versions etc.

My board version is: 0432055-04-1842 (whizzysystems.com).

The HW revision is Z1-ZCU102 Rev 1.1

I have no idea what SODIMM this board has and don't know if the above answer is applicable.

Thank you

Subu

 

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Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎06-13-2018

Re: ZCU102 Board User Interface test failed

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Hello @subu.rama,

ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with New SODIMM
(MTA4ATF51264HZ-2G6E1).

Since your board is labeled with 0432055-04-1842 (whizzysystems.com), it is shipped with the Old SODIMM part.

1. Have you tried to run the 2018.2 BIT test?

2. Please share the screenshot of the BIT GUI.

3. To upgrade the firmware please check https://www.xilinx.com/support/answers/69640.html.

Regards,

Naveen 

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Observer subu.rama
Observer
276 Views
Registered: ‎07-22-2018

Re: ZCU102 Board User Interface test failed

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Naveen:

As I mentioned in my other post I am unable to successfully update the firmware using either 2018.3 or 2019.1

I have posted various screen shots to these posts:

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU102-BOARD-UI-test-failed/td-p/998036

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU102-Rev-1-1-Board-UI-gives-error/td-p/1002910

https://forums.xilinx.com/t5/Evaluation-Boards/XTP433-running-BIT-exe-from-zcu102-scui-flash-restore-to-update/td-p/1002889

I will try 2018.2 later tonight.

Thank you

Subu

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Observer subu.rama
Observer
264 Views
Registered: ‎07-22-2018

Re: ZCU102 Board User Interface test failed

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NO success with 2018.2 version either.

Error: BSL Flashing Failed after File sent successfully.

I am running this on a Windows 10 machine.

I have a ZCU102 with the older DIMM. 0432055-04-1842

The UART drivers:  (6.7.0.0 dated 3/19/2014)

image.pngimage.png

Running the 2018.2 BIT.exe gives:

image.pngHere is the complete log from BIT.

Board: ZCU102
Serial Number: 0000-0000
Mac Address: 01:02:03:04:05:06


Info: SYS_CTLR v1.50 RESTORE test started...

Info: The test will take 0 hours, 01 minutes, and 23 seconds. 0:01:23

Info: This step started at: 2019-08-01 17:28:06

Info: This step started at: 2019-08-01 17:28:06

!! Press ESC to enter System Controller mode.

User has confirmed: "Turn ZCU102 Board Power Off.
Set mode switch SW6 to "0" (Up,Up,Up,Up)
Connect two jumpers across J164 as shown in XTP433
Turn ZCU102 Power On"

step finished 

Info: This step started at: 2019-08-01 17:28:39
after 2000

catch { disconnect }
1
after 2000

connect -url tcp:127.0.0.1:3121
attempting to launch hw_server

****** Xilinx hw_server v2018.3
  **** Build date : Dec  7 2018-00:40:27
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application



****** Xilinx hw_server v2018.3

  **** Build date : Dec  7 2018-00:40:27

    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.



INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application




INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121



tcfchan#0
targets -set -filter {name =~"*APU*"}

rst -srst

after 3000

targets -set -filter {name =~"*APU*"}

fpga -no-revision-check -file H:/XilinxDownloads/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/bitstream/boot_strap_loader.bit

initializing
  0%    0MB   0.0MB/s  ??:?? ETA
  4%    1MB   2.1MB/s  ??:?? ETA
  7%    1MB   1.8MB/s  ??:?? ETA
 11%    2MB   1.8MB/s  ??:?? ETA
 14%    3MB   1.7MB/s  ??:?? ETA
 18%    4MB   1.7MB/s  ??:?? ETA
 21%    5MB   1.7MB/s  00:11 ETA
 25%    6MB   1.7MB/s  00:11 ETA
 29%    7MB   1.7MB/s  00:10 ETA
 33%    8MB   1.7MB/s  00:09 ETA
 36%    9MB   1.7MB/s  00:09 ETA
 39%   10MB   1.7MB/s  00:08 ETA
 43%   11MB   1.7MB/s  00:08 ETA
 46%   11MB   1.7MB/s  00:07 ETA
 50%   12MB   1.7MB/s  00:07 ETA
 53%   13MB   1.7MB/s  00:06 ETA
 57%   14MB   1.7MB/s  00:06 ETA
 61%   15MB   1.7MB/s  00:05 ETA
 64%   16MB   1.7MB/s  00:05 ETA
 68%   17MB   1.7MB/s  00:04 ETA
 72%   18MB   1.7MB/s  00:04 ETA
 75%   19MB   1.7MB/s  00:03 ETA
 79%   20MB   1.7MB/s  00:03 ETA
 83%   21MB   1.7MB/s  00:02 ETA
 87%   22MB   1.7MB/s  00:01 ETA
 90%   22MB   1.7MB/s  00:01 ETA
 93%   23MB   1.7MB/s  00:00 ETA
 97%   24MB   1.7MB/s  00:00 ETA
100%   25MB   1.7MB/s  00:14    

targets -set -filter {name =~"*APU*"}

source H:/XilinxDownloads/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/tcl/bsl_psu_init.tcl

psu_init

after 1000

psu_ps_pl_isolation_removal

after 1000

psu_ps_pl_reset_config

targets -set -filter {name =~"*A53*0"}

rst -processor

dow H:/XilinxDownloads/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/elf/boot_strap_loader.elf

Downloading Program -- H:/XilinxDownloads/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/elf/boot_strap_loader.elf
	section, .text: 0x00000000 - 0x0001442f
	section, .init: 0x00014440 - 0x00014473
	section, .fini: 0x00014480 - 0x000144b3
	section, .note.gnu.build-id: 0x000144b4 - 0x000144d7
	section, .rodata: 0x000144d8 - 0x00014dcf
	section, .rodata1: 0x00014dd0 - 0x00014dff
	section, .sdata2: 0x00014e00 - 0x00014dff
	section, .sbss2: 0x00014e00 - 0x00014dff
	section, .data: 0x00014e00 - 0x00015fe7
	section, .data1: 0x00015fe8 - 0x00015fff
	section, .ctors: 0x00016000 - 0x00015fff
	section, .dtors: 0x00016000 - 0x00015fff
	section, .eh_frame: 0x00016000 - 0x00016003
	section, .mmu_tbl0: 0x00017000 - 0x0001700f
	section, .mmu_tbl1: 0x00018000 - 0x00019fff
	section, .mmu_tbl2: 0x0001a000 - 0x0001dfff
	section, .preinit_array: 0x0001e000 - 0x0001dfff
	section, .init_array: 0x0001e000 - 0x0001e007
	section, .fini_array: 0x0001e008 - 0x0001e047
	section, .sdata: 0x0001e048 - 0x0001e07f
	section, .sbss: 0x0001e080 - 0x0001e07f
	section, .tdata: 0x0001e080 - 0x0001e07f
	section, .tbss: 0x0001e080 - 0x0001e07f
	section, .bss: 0x0001e080 - 0x0011e2bf
	section, .heap: 0x0011e2c0 - 0x001262bf
	section, .stack: 0x001262c0 - 0x0012f2bf

  0%    0MB   0.0MB/s  ??:?? ETA
 79%    0MB   0.2MB/s  ??:?? ETA
100%    0MB   0.2MB/s  00:00    

Setting PC to Program Start Address 0x00000000
Successfully downloaded H:/XilinxDownloads/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/elf/boot_strap_loader.elf

con

step finished 

Info: This step started at: 2019-08-01 17:29:10
||||||||||||||||||||
File sent successfully

Error: BSL Flashing Failed

Error: Found regular expression in step 3 of test 0 - "(.*)Error(.*)"

Info: This step started at: 2019-08-01 17:29:41

Error: Stopped because step 3 failed in test 0

step finished 

Error: Could not find regular expression in step 0 of test 0 - "(.*)MSP v1.50 I2C Bridge v1.50(.*)"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Pass
Info: Result for step 3: Fail
Info: The test took 0 hours, 01 minutes, and 04 seconds. 0:01:04

The Vivado directory for BIT is pointed to the 2018.3 version. I don't have the 2018.2 version of Vivado installed.

I also tried pointing it at 2019.1 vivado with identical errors.

Only 2018.3 and 2019.1.1   (both of which fail also with various versions of the BIT from the various versions of the rdf0382 zip files).

Subu

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Observer subu.rama
Observer
249 Views
Registered: ‎07-22-2018

Re: ZCU102 Board User Interface test failed

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I even installed Vivado 2018.2 to run the 2018.2 BIT test. No success. Same "BSL Flashing failed" error.

Subu

 

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Observer subu.rama
Observer
204 Views
Registered: ‎07-22-2018

Re: ZCU102 Board User Interface test failed

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To get further insight into this issue, I installed a laptop with Windows 7 x64, installed the 6.7.0.0 of the Si drivers and tried it with 2018.2, 2018.3 and 2019.1

I do NOT get the BSL flashing failed error. BUT, the firmware is NOT updated. The MSP refuses to go beyond v1.30.

Partial log with 2018.2; Note the MSP v1.10 I2C Bridge v1.30    The defaults.json file has this pass condition. I changed it so it would "pass" when checking for the status. If I don't it fails. 

"pass condition": [
                        "(.*)MSP v1.10 I2C Bridge v1.30(.*)"
                    ], 

The pass condition when the FW is really updated (which is what is in defaults.json as shipped) is:

 "pass condition": [
                        "(.*)MSP v1.50 I2C Bridge v1.50(.*)"
                    ], 

 

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/zcu102_Xilinx/rdf0382-zcu102-system-controller-c-2018-2/zcu102_scui/flash_restore/tests/ZCU102/elf/boot_strap_loader.elf

con

step finished 

Info: This step started at: 2019-08-09 11:37:37
||||||||||||||||||||
File sent successfully


Info: This step started at: 2019-08-09 11:38:09

!! Press ESC to enter System Controller mode.

User has confirmed: "Remove the jumpers and cycle ZCU102 Board Power."

step finished 

Info: This step started at: 2019-08-09 11:38:30

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source {tcl\five_second_delay.tcl}
# after 5000
INFO: [Common 17-206] Exiting Vivado at Fri Aug  9 11:38:43 2019...
step finished 

Info: This step started at: 2019-08-09 11:38:43
Writing: '\x1b'
Writing: '\x08'
[('', 'VRN', '', '')]
Writing: '\t'
:R
Writing: 'VRN\r\t'
'\r\n!! Press ESC to enter System Controller mode.\r\n\r\n!! Press ESC to enter System Controller mode.\r\n\x08:R\r'VRN
:P
MSP v1.10 I2C Bridge v1.30

step finished 

Info: Result for step 0: Pass
Info: Result for step 1: Pass
Info: Result for step 2: Pass
Info: Result for step 3: Pass
Info: Result for step 4: Pass
Info: Result for step 5: Pass
Info: Result for step 6: Pass

 

 

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