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Visitor lucas.lima
Visitor
156 Views
Registered: ‎04-19-2019

ZCU102 not booting

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Hi, 

I'm having an issue with the boot of a brand new ZC102 board. 

When trying to boot through the SD Card, the FSBL inits but neither jumps to the main application nor loads the bitstream (init_b led goes green, some text is printed in uart, but done led keeps off). After some seconds, the init_b led goes red together with the ps_err_out. 

I have other zcu102 boards (same revision - 1.1) and the same sd card works perfectly. 

I can't run any demo code through jtag either, I'm having the following error:

Error while lauching program:

Memory read error at 0xFFCA5000. Cannot read sctr_el3. Cannot read r0. Intruction transfer timeout. 

The very same example works perfectly in the other boards.

The register values below were read before the leds went red in a SD Boot. 

xsct% source boot_registers_log_rev1_0.tcl
======================================================================
==  Registers Dump
    BOOT_MODE_USER                  = FF5E0200:   0000000E
    BOOT_MODE_POR                   = FF5E0204:   00000EEE
    RESET_REASON                    = FF5E0220:   00000001
    PMU_GLOBAL.PWR_STATE            = FFD80100:   00FFFCBF
    PWR_SUPPLY_STATUS               = FFD8010C:   00000007
    CSU_BR_ERROR                    = FFD80528:   00009292
    ERROR_STATUS_1                  = FFD80530:   00000000
    ERROR_STATUS_2                  = FFD80540:   00000000
    csu_status                      = FFCA0000:   00000000
    csu_ft_status                   = FFCA0018:   00000000
    CSU_ISR                         = FFCA0020:   00008034
    pcap_status                     = FFCA3010:   A0000A47
    tamper_status                   = FFCA5000:   00000004
    jtag_chain_status               = FFCA0034:   00000003
    jtag_sec                        = FFCA0038:   000001FF
  1  PS TAP
     2  PMU
       13* MicroBlaze PMU (Running)
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU
        9  Cortex-A53 #0 (Running)
       10  Cortex-A53 #1 (Power On Reset)
       11  Cortex-A53 #2 (Power On Reset)
       12  Cortex-A53 #3 (Power On Reset)
CONFIG STATUS: 377495308
                               CRC ERROR (Bits [0]): 0
                        DECRYPTOR ENABLE (Bits [1]): 0
                         PLL LOCK STATUS (Bits [2]): 1
                        DCI MATCH STATUS (Bits [3]): 1
             END OF STARTUP (EOS) STATUS (Bits [4]): 0
                        GTS_CFG_B STATUS (Bits [5]): 0
                              GWE STATUS (Bits [6]): 0
                            GHIGH STATUS (Bits [7]): 0
                           MODE PIN M[0] (Bits [8]): 1
                           MODE PIN M[1] (Bits [9]): 1
                          MODE PIN M[2] (Bits [10]): 1
          INIT_B INTERNAL SIGNAL STATUS (Bits [11]): 1
                             INIT_B PIN (Bits [12]): 1
            DONE INTERNAL SIGNAL STATUS (Bits [13]): 0
                               DONE PIN (Bits [14]): 0
                           IDCODE ERROR (Bits [15]): 0
                         SECURITY ERROR (Bits [16]): 0
  SYSTEM MONITOR OVER-TEMP ALARM STATUS (Bits [17]): 0
     CFG STARTUP STATE MACHINE PHASE (Bits [20:18]): 0
                     SECURITY_STATUS (Bits [23:21]): 4
                               RESERVED (Bits [24]): 0
             CFG BUS WIDTH DETECTION (Bits [26:25]): 3
                    SECURITY AUTH ERROR (Bits [27]): 0
                             PUDC_B PIN (Bits [28]): 1
                       BAD PACKET ERROR (Bits [29]): 0
                             CFGBVS PIN (Bits [30]): 0
                               RESERVED (Bits [31]): 0
xsct% Info: tcfchan#1 closed

The register values below were read after the leds went red in a SD Boot. 

source boot_registers_log_rev1_0.tcl
xsct% attempting to launch hw_server

****** Xilinx hw_server v2018.2
  **** Build date : Jun 14 2018-20:42:52
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application



****** Xilinx hw_server v2018.2

  **** Build date : Jun 14 2018-20:42:52

    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.



INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application




INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121



======================================================================
==  Registers Dump
    BOOT_MODE_USER                  = FF5E0200:   0000000E
    BOOT_MODE_POR                   = FF5E0204:   00000EEE
    RESET_REASON                    = FF5E0220:   00000005
    PMU_GLOBAL.PWR_STATE            = FFD80100:   00FFFCBF
    PWR_SUPPLY_STATUS               = FFD8010C:   00000007
    CSU_BR_ERROR                    = FFD80528:   00009292
    ERROR_STATUS_1                  = FFD80530:   00001000
    ERROR_STATUS_2                  = FFD80540:   02000000
    csu_status                      = FFCA0000:   00000000
    csu_ft_status                   = FFCA0018:   00000000
    CSU_ISR                         = FFCA0020:   00008024
    pcap_status                     = FFCA3010:   00000A02
    tamper_status                   = FFCA5000:   00000004
    jtag_chain_status               = FFCA0034:   00000003
    jtag_sec                        = FFCA0038:   000001FF
  1  PS TAP
     2  PMU
       13* MicroBlaze PMU (Running)
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU
        9  Cortex-A53 #0 (Running)
       10  Cortex-A53 #1 (Power On Reset)
       11  Cortex-A53 #2 (Power On Reset)
       12  Cortex-A53 #3 (Power On Reset)
CONFIG STATUS: 0
                               CRC ERROR (Bits [0]): 0
                        DECRYPTOR ENABLE (Bits [1]): 0
                         PLL LOCK STATUS (Bits [2]): 0
                        DCI MATCH STATUS (Bits [3]): 0
             END OF STARTUP (EOS) STATUS (Bits [4]): 0
                        GTS_CFG_B STATUS (Bits [5]): 0
                              GWE STATUS (Bits [6]): 0
                            GHIGH STATUS (Bits [7]): 0
                           MODE PIN M[0] (Bits [8]): 0
                           MODE PIN M[1] (Bits [9]): 0
                          MODE PIN M[2] (Bits [10]): 0
          INIT_B INTERNAL SIGNAL STATUS (Bits [11]): 0
                             INIT_B PIN (Bits [12]): 0
            DONE INTERNAL SIGNAL STATUS (Bits [13]): 0
                               DONE PIN (Bits [14]): 0
                           IDCODE ERROR (Bits [15]): 0
                         SECURITY ERROR (Bits [16]): 0
  SYSTEM MONITOR OVER-TEMP ALARM STATUS (Bits [17]): 0
     CFG STARTUP STATE MACHINE PHASE (Bits [20:18]): 0
                     SECURITY_STATUS (Bits [23:21]): 0
                               RESERVED (Bits [24]): 0
             CFG BUS WIDTH DETECTION (Bits [26:25]): 0
                    SECURITY AUTH ERROR (Bits [27]): 0
                             PUDC_B PIN (Bits [28]): 0
                       BAD PACKET ERROR (Bits [29]): 0
                             CFGBVS PIN (Bits [30]): 0
                               RESERVED (Bits [31]): 0
xsct% Info: tcfchan#2 closed

Thanks in advance!

Lucas

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1 Solution

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Observer wenyeliu
Observer
143 Views
Registered: ‎12-23-2018

Re: ZCU102 not booting

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Hi @lucas.lima,

I think your issue is related on the change of sodimm memory. See this AR https://www.xilinx.com/support/answers/71961.html.

Actually my board is also in the affected batch. 

All the examples/demos built by 2018.2 and older versions tools will not work.

The solution is change the DDR configuration of your ZYNQ ip in Vivado and generate a new bitstream. You can check the AR for detail configuration of the new sodimm ddr4 memory.

Generate your SD card image in new version (2018.3) SDK. That work fine for me.

If you are using SDSoc, just use the new version (2018.3) tool to rebuild the project. I find the SDSoc tutorial works on my board.

 

Regards,

Wenye

2 Replies
Highlighted
Observer wenyeliu
Observer
144 Views
Registered: ‎12-23-2018

Re: ZCU102 not booting

Jump to solution

Hi @lucas.lima,

I think your issue is related on the change of sodimm memory. See this AR https://www.xilinx.com/support/answers/71961.html.

Actually my board is also in the affected batch. 

All the examples/demos built by 2018.2 and older versions tools will not work.

The solution is change the DDR configuration of your ZYNQ ip in Vivado and generate a new bitstream. You can check the AR for detail configuration of the new sodimm ddr4 memory.

Generate your SD card image in new version (2018.3) SDK. That work fine for me.

If you are using SDSoc, just use the new version (2018.3) tool to rebuild the project. I find the SDSoc tutorial works on my board.

 

Regards,

Wenye

Visitor lucas.lima
Visitor
116 Views
Registered: ‎04-19-2019

Re: ZCU102 not booting

Jump to solution

Hi @wenyeliu ,

Thanks for your prompt reply. It seems that it was the problem. The board came with a different dimm, after changing the vivado project and updating the fsbl, the project worked again. 

Thanks!

 

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