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Visitor a_saberi
Visitor
3,169 Views
Registered: ‎11-07-2011

problem in filtering input signals []Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate Error occurred during "Block Configuration".

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],


  In the paper, I need to implement  filter

the following is the error thst I receive:

Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate
Error occurred during "Block Configuration"

 

Let me describe what I did:

I have system generator with 66.667 MHz pulse and 1/8122 sampling period

I have Sine input that is 1000Hz and has sampling rate of 1/8192

The input unit has also 1/8192 sampling period

Then ......

error ..... it mean that there is problem with my period, what time of setting I can do keep in original setting of sampling 1/8192 untouched and get the result?

 

thanks in advance

Best

Ali

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1 Reply
Xilinx Employee
Xilinx Employee
3,163 Views
Registered: ‎11-28-2007

Re: problem in filtering input signals []Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate Error occurred during "Block Configuration".

If it's possible, please open a new thread on the DSP Tools board ( http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL ) and attach your model.

 


@a_saberi wrote:

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],


  In the paper, I need to implement  filter

the following is the error thst I receive:

Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate
Error occurred during "Block Configuration"

 

Let me describe what I did:

I have system generator with 66.667 MHz pulse and 1/8122 sampling period

I have Sine input that is 1000Hz and has sampling rate of 1/8192

The input unit has also 1/8192 sampling period

Then ......

error ..... it mean that there is problem with my period, what time of setting I can do keep in original setting of sampling 1/8192 untouched and get the result?

 

thanks in advance

Best

Ali




Cheers,
Jim
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