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Visitor zjyzjy
Visitor
173 Views
Registered: ‎11-10-2018

question about kc705 eval board

in "ug810_Kc705_Eval_Bd",we can see as below,

can i use SMA Clock Input as Output?will it violate something?

sma1.PNGsma2.PNG

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3 Replies
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎03-07-2018

Re: question about kc705 eval board

Hello @zjyzjy 

I believe it is possible.

Please check this thread for more details: https://forums.xilinx.com/t5/Evaluation-Boards/ZC706-SMA-Clock-Output/td-p/815117

Regards,
Bhushan

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Visitor zjyzjy
Visitor
150 Views
Registered: ‎11-10-2018

Re: question about kc705 eval board

my verilog code:   

       module top(
              input clk_p,
              input clk_n,
              output clk_p_out,
             output clk_n_out);
 
        assign clk_p_out = clk_p;
        assign clk_n_out = clk_n;
endmodule
 
my constraints code:
     set_property PACKAGE_PIN Y12 [get_ports clk_p]
     set_property IOSTANDARD LVDS [get_ports clk_p]
     set_property PACKAGE_PIN Y11 [get_ports clk_n]
     set_property IOSTANDARD LVDS [get_ports clk_n]
     set_property PACKAGE_PIN L25 [get_ports clk_p_out]   #user_sma_clock_p
     set_property IOSTANDARD LVDS_25 [get_ports clk_p_out]
     set_property PACKAGE_PIN K25 [get_ports clk_n_out]  #user_sma_clock_n
     set_property IOSTANDARD LVDS_25 [get_ports clk_n_out]
 
but i get errors:
           [DRC IOSTDTYPE-1] IOStandard Type: I/O port clk_n is Single-Ended but has an IOStandard of LVDS which can only support Differential
 
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Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎06-21-2018

Re: question about kc705 eval board

Hy zjyzjy,

Just routing the pins from input to output will not work, you need to do Clock Forwarding.

You need to use and IBUFDS on the input and an ODDR on the output, like in this thread:
https://forums.xilinx.com/t5/Other-FPGA-Architectures/clock-generation-from-KC705-usewr-SMA-GPIO/td-p/633662

Let us know if you have questions.

Thanks,
Andres

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