01-12-2019 04:01 AM
In KC705, 200MHz system clock is in the same bank as DDR3 for reason that the memory interface generator IP core uses system clock. In my design system clock is in a HR bank and DDR3 is in HP bank. In the MIG setting, I can choose not to use clock. What is the difference for that option (use clock or not)? Will it affect the performance of DDR3?
01-12-2019 09:36 PM
The SYSCLK input on the KC705 happens to enter the FPGA in one of the banks that contains DDR interface pins. It didn't need to enter at that bank--or at either of the other banks used for the DDR interface. It could have entered the chip at any bank, using a clock-capable pin to get to a BUFG.
I'm not sure what you mean by "I can choose not to use clock". The MIG needs a clock. In the MIG wizard, a selection is offered that allows one to prevent the insertion (inside the generated MIG core) of an IO buffer on the SYSCLK input, but a clock must be provided nonetheless.
You are highly encouraged to use an external clock (from a low-jitter source) as the SYSCLK of your MIG. Ideally, the clock should enter your FPGA at a clock-capable pin. Your memory performance could be adversely affected if you instead use an internally generated clock for the MIG's SYSCLK.
01-14-2019 02:03 AM
There is an option for system clock in MIG: "single-ended", "differential", and "no buffer". If I choose no buffer, the following step would not ask me to choose the clock pin location. If I choose differential or single ended, the following steps require me to choose the pin number. And the pin number is only limited to ddr3 address/control bank or the adjacent bank. I have no idea if it is better to choose no buffer and be free to put system clock of FPGA in MRCC pins of any bank. What is the difference to choose no buffer and orhers? Which is the better choice. My PCB is not designed, so I also can change my clock pin location.
01-14-2019 04:54 AM
The "no buffer" option just means the MIG generator will not include an IO buffer (single-ended or differential) on that clock line inside the core it creates. That core still needs a clock, though. If you choose the "no buffer" option, you'd be expected to drive the core's SYSCLK input with an external clock for which you've already included an appropriate IO buffer elsewhere in your design. (This option is provided so that a SYSCLK input can be shared with another MIG core, or another IP that uses the same clock.)
Let me clarify a statement I made earlier: "[SYSCLK] could have entered the chip at any bank in the same IO column that contains the DDR interface, using a clock-capable pin to get to a BUFG." Since the DDR interface of the K7 on the KC705 uses all of the banks in a column, the clock placement location in that case will coincide the one of those banks.
If the HR bank you're using (to receive your external system clock) is in the same IO column as the HP banks you're using for your DDR interface, then you should be good. Otherwise, you should move the SYSCLK input to a clock-capable pin in the same column as the DDR interface.
01-14-2019 05:25 AM