07-31-2019 03:56 AM
I have the zcu106 Rev 1.0 evalution board and I'm using the Vivado 2019.1 ( with updates for 2019.1.1) on Ubuntu 18.04.2 LTS
I have tried to build the "new" design module 11 , pl/scripts/hdmi_plddr_proj.tcl
and it fails with the message
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
I left it to complete the synthesis stage and I got this error
hdmi_plddr_v_frmbuf_rd_0_1_synth_1 Out-of-date Due to
hdmi_plddr_v_frmbuf_rd_0_1_synth_1 – IP modified.
Help on how to overcome this issue would be appricated.
I had previously tried pl/scripts/vcu_trd_proj.tcl but it failed , so I thought it best to try the latest design module 11 which is new to the Vivado 2019.1 for the zcu106 evaluation board . Please note I have the 2019.1 and also the updates for 2019.1.1
08-05-2019 08:09 AM
Ubuntu 18.04.2 LTS is not a supported OS for Vivado 2019.1. Can you try with Ubuntu 18.04.1 LTS? (reference UG973)
If the doesn't help, could you check the vivado_hls.log file under the frame buffer output prducts (can you share it as well). It might contains an error from vivado HLS (which is building the IP under the hood)
08-12-2019 09:38 PM
Do you have an update on this? Let us know if you have follow up queries.
08-13-2019 12:39 AM
I will downgrade my Ubuntu from 18.04.02 to 18.04.01 and see if these reference build. I was on PTO thus the delay in responding