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Observer huhanvictory
Observer
2,924 Views
Registered: ‎06-26-2014

zedboard DDR address

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I want to test DDR read/write on zedboard. The size of DDR on zedboard is 512M. According to UG585, the address assigned to DDR is from 0x00100000 to 0x3fffffff, which is 1023M.

My design is as follows:

1. Write 32bit-data to address 0x00100000-0x3fffffff from PL side.

2. When writing operation is done, start to read data in address 0x00100000-0x3fffffff from PL side.

 

The data read from DDR is compared with the data written into DDR. The results are as follows:

1. data read from 0x30000000-0x3fffffff is correct

2. data read from 0x20000000-0x20080000 is correct

3. data read from other address has some wrong bits in the high 5 bits

 

So I want to know how to choose the proper address for the 512M DDR. Besides, since I used the DDR controller in PS, I'm not sure whether the code in PS will occupy some DDR address or not.

Is anyone able to solve my problem? Thanks.

I am a freshmen of FPGA. But I know everything is ok if I work hard.
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1 Solution

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Teacher muzaffer
Teacher
4,232 Views
Registered: ‎03-31-2012

Re: zedboard DDR address

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@huhanvictory you are probably doing these tests in bare-metal in which case the addresses used by the PS & PL to refer to  the same ddr location are the same. Your problem is most probably related to caching issues. You need to flush the cache when you write from PS before PL can read it and you need to invalidate the cache when you write from PL before PS can read it. This assumes you are using one of the HPx ports and not the ACP.

 

You can use these functions:

 

Xil_DCacheFlush and Xil_DCacheInvalidate

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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5 Replies
Teacher muzaffer
Teacher
4,233 Views
Registered: ‎03-31-2012

Re: zedboard DDR address

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@huhanvictory you are probably doing these tests in bare-metal in which case the addresses used by the PS & PL to refer to  the same ddr location are the same. Your problem is most probably related to caching issues. You need to flush the cache when you write from PS before PL can read it and you need to invalidate the cache when you write from PL before PS can read it. This assumes you are using one of the HPx ports and not the ACP.

 

You can use these functions:

 

Xil_DCacheFlush and Xil_DCacheInvalidate

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Observer novec_16
Observer
2,797 Views
Registered: ‎04-25-2017

Re: zedboard DDR address

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Dear @huhanvictory  please help me to understand how it is possible to write and read from the address space beyond the space of RAM available on your board?

Thanks!

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Observer huhanvictory
Observer
1,931 Views
Registered: ‎06-26-2014

Re: zedboard DDR address

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First, a self-defined IP is require to control the address of read and write. (Open vivado, Tools-Create and Package New IP-Create a new AXI4 peripheral). Then you could use axi_mem_interconnect to map the address to ddr in Processing System. 

Hope it is helpful for you.

I am a freshmen of FPGA. But I know everything is ok if I work hard.
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Observer yqq654101
Observer
911 Views
Registered: ‎04-15-2018

Re: zedboard DDR address

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I want to write/read data from DDR using s-axi-gp0,but ps has been writen data to DDR,but pl write same data in same address,can you please tell me why
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Observer yqq654101
Observer
910 Views
Registered: ‎04-15-2018

Re: zedboard DDR address

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want to write/read data from DDR using s-axi-gp0,ps has been writen data to DDR,but pl read eeor data in same address,can you please tell me why
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