cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
666 Views
Registered: ‎06-24-2019

7-series FPGA functional safety, FIT estimation

Hello Functional safety expert :)

For our project we are using XA7A50T-CSG324 which has no bonding to PCIe and GTPs

Here I have few questions for you regarding FIT rate estimation.

1) When I use TCL scripts for FIT rate estimation, Does evaluation of unused cells include FIT rate of PCIe and GTPs ?

2) If PCIe and GTPs are still on Silicon, how do they contribute to FIT rate (using tcl scripts)?

  • Do they always considered as/in unused blocks?
  • Is it safe to consider them as safe blocks for our analysis, since they are not used

3) Which temperature mission profile is assumed in calculating FIT ? (using thes tcl file)

4) Diagnostic coverage: logic monitoring, SEM IP, BRAM- parity,ECC. what is the recommended diagnostic coverage (%) for these safety mechanisms?

5) What could happen to FPGA, if there is no OV/UV montoring, temp monitoring implemented in XADC block? destruction of FPGA or does FPGA go to reset mode or malfunction?  

Thank you and we look forward to your quick reply.

Best regards,

Shashank

0 Kudos
Reply
3 Replies
648 Views
Registered: ‎09-17-2018

ss,

First, the hardware failure rate is given in ug116 for 7 series, it is the worst case number for any device in the 28nm technology node.  Page 29, 11 FIT.

The FIT for soft errors is on page 31 (CRAM) and 32 (BRAM).  Use the SEU Estimator Spreadsheet for what your device, and usage.

Answers:

1) When I use TCL scripts for FIT rate estimation, Does evaluation of unused cells include FIT rate of PCIe and GTPs ?

No unused cells are included in soft FIT.

2) If PCIe and GTPs are still on Silicon, how do they contribute to FIT rate (using tcl scripts)?

They do not contribute to soft FIT.

3) Which temperature mission profile is assumed in calculating FIT ? (using thes tcl file)

For hard FIT, max recommended voltages, max recommended temperatures.  Does not affect SEU FIT.

4) Diagnostic coverage: logic monitoring, SEM IP, BRAM- parity,ECC. what is the recommended diagnostic coverage (%) for these safety mechanisms?

The SEM IP covers 100% of CRAM, 0% of BRAM.  ECC in BRAM is recommended for any safety critical system.  It is up to you to arrange to write back when an error is corrected upon read.

5) What could happen to FPGA, if there is no OV/UV montoring, temp monitoring implemented in XADC block? destruction of FPGA or does FPGA go to reset mode or malfunction?

Under what assumptions?  If I exceed the abs max specs, I risk device destruction - nothing you do can change that.  If I hit it with a hammer, no amount of coding protects it.  Assumptions of use are critical to a safe system design.  The XADC can be a useful way to detect the system is entering into an unsafe condition.  The rest is up to you.

l.e.o.

 

Tags (1)
0 Kudos
Reply
557 Views
Registered: ‎06-24-2019

Thank you!

counter questions below

1) When I use TCL scripts for FIT rate estimation, Does evaluation of unused cells include FIT rate of PCIe and GTPs ?

No unused cells are included in soft FIT.

Then what does unused FIT rate includes/means?

2) If PCIe and GTPs are still on Silicon, how do they contribute to FIT rate (using tcl scripts)?

They do not contribute to soft FIT.

How much do they contribute to Hard FIT? 

3) Which temperature mission profile is assumed in calculating FIT ? (using thes tcl file)

For hard FIT, max recommended voltages, max recommended temperatures.  Does not affect SEU FIT.

It means permanent FIT= 11FIT @55 deg or 125deg? (According to UG116). Could you please briefly explain, why temp profile doesn't affect SEU FIT (transient FIT)?

6) Do XILINX has a Failure mode analysis done on Hard FIT (Hardware) as a reference example?

Regards,

Shashank.

0 Kudos
Reply
545 Views
Registered: ‎09-17-2018

s,

As I am no longer a Xilinx employee (their loss), so you need to contact your Xilinx distributor, and request a reliability presentation.  After signing the NDA, they will educate you.

l.e.o.

0 Kudos
Reply