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Observer
Observer
9,925 Views
Registered: ‎11-14-2013

7 series fpga SPI and ganged serial daisy chain configuration

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Hello buddy,

 

I have a custom board with 5 A75T FPGAs.

I want to configure 5 FPGAs all from 1 SPI Flash, where the master uses a unique bit file and the rest of the downstream FPGAs use the same bit file. Therefore, 2 bit streams total in the SPI Flash.

 

So the first A75T is attached with a spi flash in master spi mode,

and the another 4 downstream A75Ts are tied together in ganged slave serial mode.

The CCLK pins of all 5 FPGAs are tied together,the DOUT pin of master A75T is tied to DIN pins of all 4 downstream A75Ts.All Done pins are tied together too.

 

I can create a mcs file with 2 bitstreams from vivado tcl command.

Programing SPI flash with the created MCS file is passed,but can't get boot.

I tried to disconnet first FPGA Done and init_b pin from others,and program spi flash with only a master bit stream,the master FPGA works.

 

My question is, are there any tricks in bit stream?

 

 

 

 

 

 

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Observer
Observer
17,248 Views
Registered: ‎11-14-2013

Hi Krishna,

 

 

I finally solved this problem.

 

1.Pull high and Pull Down 330ohm resistor on CCLK to keep SI

2.create slave fpga bit file in Master SPI mode instead of slave serial mode

3.Create MCS file in the order  "Master FPGA bit + downstream FPGA bit"

4.Don't enable serial stream debug mode in GUI

 

 

Regards,

 

 

Kim

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Xilinx Employee
Xilinx Employee
9,921 Views
Registered: ‎08-01-2012

You mentioned that "DOUT pin of master A75T is tied to DIN pins of all 4 downstream A75Ts". That is not correct in daisy chain.

 

The DOUT of first  FPGA should connect to DIN of second FPGA. The DOUT out put of that second  FPGA should be connected to DIN of next third  FPGA like that.

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Moderator
Moderator
9,914 Views
Registered: ‎01-15-2008

Hello Kimwen,

 

can you capture the status registers of the first fpga and the second fpga and attach to this thread.

we can have a look.

how are the done pins connected for all the fpgas?

 

--Krishna

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Community Manager
Community Manager
9,912 Views
Registered: ‎07-23-2012
Hi Kimwen,

It looks like you are trying to combine serial daisy chain (for master) with ganged serial mode. This is something which we didn't test.

Regards,
Krishna
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Observer
Observer
9,891 Views
Registered: ‎11-14-2013

Hi Krishna,

 

I connected all 5 FPGAs Done Pins togerther and pull high with a 4.7K resistor.

After boot fail,I tried to only download bit stream to slave FPGAs via JTAG cable,the Mater got work!

It shows the slave FPGAs Done pin is Low.

 

I found the Master FPGA DOUT data from my oscilloscope begins with " 0xAA, 0x99,0x55,0x66....".

It seems the problems is. As I known, the slave serial data should be bit swapped,right?

 

How can I use TCL tools to combine a SPI bit file(no bit swapped ) with a slave serial bit file(bit swapped) into a MCS file?

 

I can only use the following command to create a config_demo.mcs

 

write_cfgmem -format MCS -size 16 -interface SPIx1 -loadbit "up 0x0 H:/my_slave_serial_test.bit  H:/my_master_spi_test.bit"  config_demo

 

Can I have any work around solution?

 

Best Regards,

 

Kim

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Community Manager
Community Manager
9,880 Views
Registered: ‎07-23-2012
Can you please share the block diagram of your setup?

Regards,
Krishna
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Observer
Observer
17,249 Views
Registered: ‎11-14-2013

Hi Krishna,

 

 

I finally solved this problem.

 

1.Pull high and Pull Down 330ohm resistor on CCLK to keep SI

2.create slave fpga bit file in Master SPI mode instead of slave serial mode

3.Create MCS file in the order  "Master FPGA bit + downstream FPGA bit"

4.Don't enable serial stream debug mode in GUI

 

 

Regards,

 

 

Kim

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