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Adventurer
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Registered: ‎03-28-2020

A problem about partially reconfigurable design based on TFTP (vu37p)

 

Hello everyone, we are trying to refer to the case ideas of example3 in xapp1292 to implement a partially reconfigurable design based on TFTP on vu37p. The development environment is VIVADO2019.1

First of all, we built part of the reconfigurable project according to the steps of ug947, and generated several partially reconfigurable bitstream files. When we directly load these partially reconfigurable bitstream files in the download tool of VIVADO, it can run successfully.

But when I use Microblaze+HWICAP to write to the dynamic logic area of vu37p through ICAPE3 primitives, although the bitstream files are normally TFTP transferred, they are successfully written without packet loss or errors. The primitive input port of ICAPE3, but when the bitstream file is completely written, the dynamic area of the FPGA has not changed any state, and it is still working in the initial state, and it seems that nothing has happened.

wuyouniyanhu_0-1603106331901.png

(With the help of wireshark and VIVADO's ILA tools, we checked each data packet sent from the TFTP server and finally reached the input port of ICAPE3)

 

 

I would like to ask experts and teachers in our forum:

Regarding the process of partial reconfiguration, after all the partially reconfigurable bitstream files are imported into ICAPE3, what should be done to complete the entire partial reconfiguration process? What are the possible causes of errors in our project?

 

Our SDK code can be obtained from here:https://github.com/wuyouniyanhu/PR_Lwip211.git

 

 

The hardware block design of VIVADO is as follows

 

 

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