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Visitor
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Registered: ‎07-14-2020

AXI Interconnect 2.1 with Custom Slave / Multiple Master Configuration, Slave not responding.

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I am using the AXI Interconnect 2.1 with a custom master-slave connection. By custom I mean I wrote the code for them myself, so the only IP generated by Xilinx is the Interconnect. My layout is 3 masters and 6 slaves (so on the interconnect I have 3 slave interfaces and 6 master interfaces) . The problem I am having is when I incorporate multiple masters in the design. i.e. I have tried the same setup with 1 master and 6 slaves and I could get the slaves to respond with no issue, then when I incorporate the other masters the slaves don't give a response for reads or writes or even the valid/ready bits on the slave side. My thought is that I have not set a specific bit to prevent the masters from locking, but I cannot find anything in the interconnect documentation specific to a bit that needs to be set when working with multiple masters. The issue is specific to when I incorporate multiple masters. so if anyone has any experience with this or needs more information please let me know. TYIA

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Scholar
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Registered: ‎03-28-2016

@FPGAking1214 

You might want to add the AXI Protocol Checker to your system to verify that your transactions meet the AXI specification.

https://www.xilinx.com/support/documentation/ip_documentation/axi_protocol_checker/v2_0/pg101-axi-protocol-checker.pdf

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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Registered: ‎03-28-2016

@FPGAking1214 

You might want to add the AXI Protocol Checker to your system to verify that your transactions meet the AXI specification.

https://www.xilinx.com/support/documentation/ip_documentation/axi_protocol_checker/v2_0/pg101-axi-protocol-checker.pdf

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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