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Registered: ‎08-20-2019

Are there situations in which dynamic total reconfiguration shall be preferred to partial reconfiguration?

Hello Xilinx users,

I am wondering in which cases (if any) total reconfigurations shall be preferred to partial reconfigurations.

This choice is important since the strategy of tasks' scheduling may change a lot according to reconfiguration time.

Is partial reconfiguration ALWAYS better than total reconfiguration or are there any domain for which it is not true?

My question is valid for any FPGA family (ultrascale, 7-family, 5-family etc) and for any domain. Even a single example in a particular domain could be useful for me to understand better this.

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Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

It depends whether you need to keep FPGA still functioning - such as keep communication with some other device; remain perform some tasks while upgrade, etc.

If the design does not these at all, you can use reconfiguration - that's always much easier, mush more safe.

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Registered: ‎08-20-2019

Hello, thanks.
Can I ask you what do you mean with "much more safe"? I think we are close to the solution.
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