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Registered: ‎08-06-2019

Artix 7 FPGA Power Up Sequence

While in the process of powering up the VCCINT, VCCAUX of the Artix 7, because the Artix 7's I/O pins were driven by other 3.3V circuitry, 3.3V was seen at the VCCO pin although I have not provided power (3.3V) to the VCCO pins yet.

My question is, if none of the Artix 7's FPGA power pins are provided with power yet, and other circuitries connected to the FPGA 3.3V I/O pins are driving the FPGA 3.3V I/O pins, is this acceptable? Will this wake up the FPGA and I see a 3.3V on its VCCO pins (and violate the power sequencing rules since VCCO is supposed to be powered up last?)

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Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

It's 'OK' if you violates the recommended power sequence as the consequences are: 1. I/O not in tri-state; 2. excessive power draw during power up.

The problem is that you may violate the Vcco-Vccaux request - check p8 of ds164. If this cannot meet, there is a possibility that device gets broken.

Don't forget to reply, kudo, and accept as solution.
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