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Scholar dgisselq
Scholar
10,427 Views
Registered: ‎05-21-2015

Artix-7 ICAPE2 and STARTUPE2

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I'm trying to work with the multiboot capabilities of the ARTIX-7 through the ICAPE2 interface.  Eventually, I'd like to be able to program a second image in the flash (in addition to a fallback already programmed) and configure from it via the warm start.  This means that I need access to the CCLK pin (to read/write/program the SPI flash), available through STARTUPE2, as well as the ICAPE2 primitive.

 

To date, while my design builds, none of the interaction with the ICAPE2 primitive seems to do anything.  My logic looks like: (before bit swapping within each byte of I)

 

CS=1, RDWRB=0, I=32'hffffffff // Dummy word, transitioning to RDWRB=0

CS=0, RDWRB=0, I=32'hffffffff // Dummy word, first word written to interface

CS=0, RDWRB=0, I=32'h000000bb // Bus width detection, 32 bit bus (X32)

CS=0, RDWRB=0, I=32'h11220044

CS=0, RDWRB=0, I=32'hffffffff // Another dummy word

CS=0, RDWRB=0, I=32'haa995566

CS=0, RDWRB=0, I=32'h20000000

CS=0, RDWRB=0, I=32'h2800e001 // Read status register (as an example)

CS=0, RDWRB=0, I=32'h20000000 // NOOP

CS=0, RDWRB=0, I=32'h20000000 // NOOP

CS=1, RDWRB=0, I=32'h20000000 // Interface deactivated

CS=1, RDWRB=1, I=32'h20000000 // Change RDWRB to read mode

CS=0, RDWRB=1, I=32'h20000000 // Wait one cycle

CS=0, RDWRB=1, I=32'h20000000 // Wait a second cycle

CS=0, RDWRB=1, I=32'h20000000 // Third wait cycle--should see answer now

CS=1, RDWRB=1, I=32'h20000000 // Deactivate interface

CS=1, RDWRB=0, I=32'h20000000 // Change RDWRB to write mode

CS=0, RDWRB=0, I=32'h30008001 // Issue a command

CS=0, RDWRB=0, I=32'h0000000d // DESYNC command

CS=0, RDWRB=0, I=32'h20000000 // NOOP

CS=0, RDWRB=0, I=32'h20000000 // NOOP

CS=1, RDWRB=0, I=32'h20000000 // Deactivate interface

 

At this point, I'm at a loss regarding what I am doing wrong.  Nothing I do changes the ICAPE2 output--it's a constant 32'ffffffdb.  Waiting extra cycles doesn't change it (up to 5), adding extra NOOPs after the read command doesn't change it.  Nothing I do changes this value.

 

So, I'll ask, is it possible that I'm struggling because I have the STARTUPE2 primitive running as well in order to control the SPI flash on my board?  Does the CCLK (i.e. SPI flash clock) need to be active for any of this to work?  Or am I missing something somewhere else?

 

Thanks!

 

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1 Solution

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Xilinx Employee
Xilinx Employee
16,635 Views
Registered: ‎10-11-2007

Re: Artix-7 ICAPE2 and STARTUPE2

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You simply need to get the bitstream, swapping and control right. I currently don't have the bandwidth to check, but, for example, you issue the bus width detection in your code. It shouldn't matter, but that is only for parallel (8/16/32) config.

View solution in original post

11 Replies
Scholar dgisselq
Scholar
10,398 Views
Registered: ‎05-21-2015

Re: Artix-7 ICAPE2 and STARTUPE2

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This link is the one that has me concerned.  It suggests that ICAPE2 and STARTUPE2 cannot be used in the same design, but the context is just simulation and not synthesis.  Is it true that these cannot be used in the same design during synthesis as well?  Are there limitations associated with using them in the same design?

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Xilinx Employee
Xilinx Employee
10,388 Views
Registered: ‎10-11-2007

Re: Artix-7 ICAPE2 and STARTUPE2

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Of course you can use both of those in the same design. The other forum discussion only relates to the simulation of the GSR function (which you probably shouldn't be using in the first place). For synthesis these are simply instantiations and in hardware they are independant, seperate blocks whith no co-dependencies.

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Scholar dgisselq
Scholar
10,378 Views
Registered: ‎05-21-2015

Re: Artix-7 ICAPE2 and STARTUPE2

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Well, thanks for the quick reply, but that leaves me as stuck as before.

 

I'm attaching my ICAPE2 interaction module.  If you have the opportunity, I'd appreciate it if you could take a peek at it and tell me if you see any errors.

 

Thanks.

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Xilinx Employee
Xilinx Employee
10,368 Views
Registered: ‎10-11-2007

Re: Artix-7 ICAPE2 and STARTUPE2

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It sounds like you want to eventually warm boot via ICAP. Then take a look at the attached. Sorry, it's in VHDL.

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Xilinx Employee
Xilinx Employee
10,363 Views
Registered: ‎10-11-2007

Re: Artix-7 ICAPE2 and STARTUPE2

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Ops. Here you go

 

----------------------------------------------------------------------------------------------

-- 7-Series reset/reconfiguration via ICAPE2.

 

library work;

 

library IEEE;

use IEEE.std_logic_1164.all;

 

library UNISIM;

use UNISIM.vcomponents.all;

 

entity iprog_rst is

  generic (

    WBSTAR  : std_logic_vector(31 downto 0) := x"00000000"     -- insert your warm boot address here

  );

  port (

    RST     : in  std_logic;

    CLK     : in  std_logic;

    RIP     : out std_logic

  );

end iprog_rst;

 

architecture arch_iprog_rst of iprog_rst is

 

   constant  CMAX    : integer := 32;

   signal  count     : integer range 0 to CMAX := 0;

   signal  run       : std_logic := '0';

   signal  cs_l      : std_logic := '1';

   signal  r_wx      : std_logic := '1';

   signal  data      : std_logic_vector(31 downto 0);

   signal  d_swapped : std_logic_vector(31 downto 0);

 

 

begin

 

process(CLK)

begin

   if(CLK'event and CLK='1') then

      if(RST = '1')  then

         run      <= '1';

      end if;

 

      if(run = '0')  then

         RIP      <= '0';

         cs_l     <= '1';

         r_wx     <= '1';

         count    <= 0;

         data     <= (others => '1');

      else

         RIP      <= '1';

 

         if(count /= CMAX)  then

            count <= count + 1;

         end if;

 

         case count is

            when  0 => data <= x"FFFFFFFF";   -- Dummy Word

            when  1 => data <= x"FFFFFFFF";   -- Dummy Word

            when  2 => data <= x"FFFFFFFF";   -- Dummy Word

            when  3 => data <= x"FFFFFFFF";   -- Dummy Word

            when  4 => data <= x"FFFFFFFF";   -- Dummy Word

            when  5 => data <= x"20000000";   -- Type 1 NO OP

               cs_l  <= '0';

               r_wx  <= '0';

            when  6 => data <= x"AA995566";   -- Sync Word

            when  7 => data <= x"20000000";   -- Type 1 NO OP

            when  8 => data <= x"20000000";   -- Type 1 NO OP

            when  9 => data <= x"30020001";   -- Type 1 Write 1 Word to WBSTAR

            when 10 => data <= WBSTAR;        -- Warm Boot Start Address

            when 11 => data <= x"20000000";   -- Type 1 NO OP

            when 12 => data <= x"20000000";   -- Type 1 NO OP

            when 13 => data <= x"30008001";   -- Type 1 Write 1 Words to CMD

            when 14 => data <= x"0000000F";   -- IPROG Command

            when 15 => data <= x"20000000";   -- Type 1 NO OP

            when 16 => data <= x"20000000";   -- Type 1 NO OP

               cs_l     <= '1';

               r_wx     <= '1';

            when others =>

               cs_l     <= '1';

               r_wx     <= '1';

         end case;

      end if;

   end if;

end process;

 

 

d_swapped(31)     <= data(24);

d_swapped(30)     <= data(25);

d_swapped(29)     <= data(26);

d_swapped(28)     <= data(27);

d_swapped(27)     <= data(28);

d_swapped(26)     <= data(29);

d_swapped(25)     <= data(30);

d_swapped(24)     <= data(31);

 

d_swapped(23)     <= data(16);

d_swapped(22)     <= data(17);

d_swapped(21)     <= data(18);

d_swapped(20)     <= data(19);

d_swapped(19)     <= data(20);

d_swapped(18)     <= data(21);

d_swapped(17)     <= data(22);

d_swapped(16)     <= data(23);

 

d_swapped(15)     <= data(8);

d_swapped(14)     <= data(9);

d_swapped(13)     <= data(10);

d_swapped(12)     <= data(11);

d_swapped(11)     <= data(12);

d_swapped(10)     <= data(13);

d_swapped(9)      <= data(14);

d_swapped(8)      <= data(15);

 

d_swapped(7)      <= data(0);

d_swapped(6)      <= data(1);

d_swapped(5)      <= data(2);

d_swapped(4)      <= data(3);

d_swapped(3)      <= data(4);

d_swapped(2)      <= data(5);

d_swapped(1)      <= data(6);

d_swapped(0)      <= data(7);

 

 

ICAPE2_inst: ICAPE2

generic map (

   ICAP_WIDTH => "X32"  -- Specifies the input and output data width.

)

port map (

   O     => open,       -- 32-bit output: Configuration data output bus

   CLK   => CLK,        -- 1-bit input: Clock Input

   CSIB  => cs_l,       -- 1-bit input: Active-Low ICAP Enable

   I     => d_swapped,  -- 32-bit input: Configuration data input bus

   RDWRB => r_wx        -- 1-bit input: Read/Write Select input

);

 

end arch_iprog_rst;

 

Scholar dgisselq
Scholar
10,359 Views
Registered: ‎05-21-2015

Re: Artix-7 ICAPE2 and STARTUPE2

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Sure, I'll try that, ... but I was hoping to be able to read from the port in addition to writing to it.  You know, something to give me an assurance that the various commands I was issuing actually worked before I jumped all the way to a warm boot.  It's the reading, before I got to the writing, that I was having problems with. (Writing wasn't working yet either, but it was next on my list.)

 

 

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Xilinx Employee
Xilinx Employee
16,636 Views
Registered: ‎10-11-2007

Re: Artix-7 ICAPE2 and STARTUPE2

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You simply need to get the bitstream, swapping and control right. I currently don't have the bandwidth to check, but, for example, you issue the bus width detection in your code. It shouldn't matter, but that is only for parallel (8/16/32) config.

View solution in original post

Scholar dgisselq
Scholar
10,264 Views
Registered: ‎05-21-2015

Re: Artix-7 ICAPE2 and STARTUPE2

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Many thanks for the help!  Much to my surprise, the code you posted was the final straw in what I needed to figure out what was going on.  I now have working verilog code that works with this interface.  While it may not be perfect, or as tight as it could be, it does work.

 

Further, for the sake of your readers and others who may be struggling with the same thing, I'm attaching my working verilog code to this message.  (Why?  Because of everyone else who attaches their broken verilog code, whose code I read while trying to get this thing to work ...)

 

Thank you again!

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2,541 Views
Registered: ‎01-30-2014

Re: Artix-7 ICAPE2 and STARTUPE2

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dgisselq,

 

Thanks for posting your Verilog Wishbone code.  I like your approach, but I needed it in VHDL.  I translated it, simplified the Wishbone pieces a little so it would fit into my Wishbone system and it ran exactly as you described.  Thanks again for the post.  Attached are my modifications.

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Explorer
Explorer
1,475 Views
Registered: ‎12-12-2009

Re: Artix-7 ICAPE2 and STARTUPE2

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@ralfk Based on the design you provided, can this procedure also be used to download a partial bitstream from SPI Flash memory? I tried something but it didn't work.

abdullah
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Newbie sassi
Newbie
243 Views
Registered: ‎11-28-2019

Re: Artix-7 ICAPE2 and STARTUPE2

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For me it does not work, do nothing.. :(

I have tried clk as 100Mhz, and than slower via a counter. No results.

What should be clk? 1Khz? 1Mhz? 100Mhz? A have not found any information about it.

What sould I do to solve it?

 

--

sassi

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