Artix-7 ICAPE2 configuration

[georgemiles]

I am using a pcie interface to write to some control registers that will ultimatley control an FSM for the ICAPE2 interface.

I am trying to simulate the device by reading from either the IDCODE or STAT registers.

I assert and deassert cs every write and read.

I am performing the bitswap metioned by ug470 and using the sequence in 32bit mode:

FFFFFFFF            Dummy Word

000000BB           Bus Width Sync Word
11220044            Bus Width Detect
FFFFFFFF            Dummy Word
AA995566            Sync Word
20000000            NOOP
2800E001            Write Type1 packet header to read STAT register
20000000            NOOP
20000000            NOOP
SSSSSSSS         Device writes one word from the STAT register to the configuration interface
30008001            Type 1 Write 1 Word to CMD
0000000D           DESYNC Command
20000000            NOOP
20000000            NOOP

However, I get the value of FFFFFFFF from both registers.

[austin]

g,

The simulation model of ICAP is not sophisticated enough to model what the configuration machine does (it it greatly simplified to help check connectivity).

You will need to run the actual bitstream to test it,

[georgemiles]

So the unisim model is garbage? What is the recommended test procedure for verifiying timing then? Chipscope and probe on test hardware?

[pratham]

@georgemiles I am not sure but i think there is an example of reading IDCODE using ICAPE2 here, please download  7 series model and check

http://www.xilinx.com/support/answers/53632.html

[georgemiles]

Thanks! So it can be simulated.

My next question is, does cs have to stay high between words sent to the icap or can i deassert it after i send each word. I am trying less for a specific setup and more for a software oriented control, i.e. I tell a controller by pcie to send this word and write.

[austin · Accepted solution]

g,

The configuration is complex.  It is not modeled completely.  All of the behaviors are just too complex for a 'perfect' model, so the model should be used for functional and connectivity verification.  To model the behavior of the configuration with timing accuracy and how it affects the actual configuration is still a goal (not fufilled as yet).

It is a static state machine.  As long as the timing in the data sheet is met, you should be able to de-assert CS between operations (completed frames or actions).