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Registered: ‎05-30-2018

Artix-7 eFuse programming

hey,
I have a question regarding the FUSE_USER configuration in the EFUSEs of an Artix-7 FPGA without enabling Bitstream encryption.

(TCL similar to AR#63206)

program_hw_devices -user_efuse {EEDDCC45} [lindex [get_hw_devices] 0]
get_property REGISTER.EFUSE.FUSE_USER [current_hw_device]
program_hw_devices -control_efuse {10} [lindex [get_hw_devices] 0]
verify_hw_devices -user_efuse {EEDDCC45}

If I anderstand it right this tcl sequence programm the EFUSE->FUSE_USER bits which can be read from the FPGA logic via EFUSE_USR primitive without enabling the bitstream encryption and disable the readback of the EFUSE->FUSE_USER bits via JTAG?

Thanks in advance.
Florian

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Artix-7 eFuse programming

When you program bit 4 of CNTL, you disable reading of user code as well as programming of AES key and user
code.

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