cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
6,877 Views
Registered: ‎07-10-2008

Artix 7 master SPI question

Jump to solution

I am wondering if the INIT_B pins of Artix 7 could be controlled as in Master BPI configuration mode to delay the FPGA configuration.

Master SPI configuration.pngMaster BPI timing.png

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
12,414 Views
Registered: ‎02-22-2010

Re: Artix 7 master SPI question

Jump to solution

UG470 under Power-on Sequence Precautions  in the Master SPI Configuration Mode explicetely states:

 

"Hold the FPGA_INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure. Release..."

View solution in original post

3 Replies
Highlighted
Explorer
Explorer
12,415 Views
Registered: ‎02-22-2010

Re: Artix 7 master SPI question

Jump to solution

UG470 under Power-on Sequence Precautions  in the Master SPI Configuration Mode explicetely states:

 

"Hold the FPGA_INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure. Release..."

View solution in original post

Highlighted
Xilinx Employee
Xilinx Employee
6,862 Views
Registered: ‎07-31-2012

Re: Artix 7 master SPI question

Jump to solution

Hi,

 

Yes you can delay configuration after power up by holding INIT_B low.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Highlighted
Explorer
Explorer
6,855 Views
Registered: ‎07-10-2008

Re: Artix 7 master SPI question

Jump to solution
Great.

Many thanks for your generous help.

0 Kudos