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Visitor
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Registered: ‎10-12-2016

Artix 7 resetting on multiboot

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I'm trying to implement Multiboot on an Artix-7 25T with SPI flash.
I have created a golden image, which I have programmed to the flash. The update image will be at address 0x140000, but I have not yet programmed it. So I excpect that the FPGA should start reading the first bytes of the golden image at address 0, then jump to 0x140000 to find that the flash is empty there, and then give up and jump back to boot from the golden image. But it doesnt't boot at all.
Timer value is set to 0x3FFFFFFF (the maximum 30-bit value).

The beginning of the golden image looks like this:
00000008: [5] ffffffff Dummy pad word
0000000C: [5] ffffffff Dummy pad word
00000010: [5] ffffffff Dummy pad word
00000014: [5] ffffffff Dummy pad word
00000018: [5] ffffffff Dummy pad word
0000001C: [5] ffffffff Dummy pad word
00000020: [5] 000000bb Bus width auto detecct, word 1
00000024: [5] 11220044 Bus width auto detecct, word 2
00000028: [5] ffffffff Dummy pad word
0000002C: [5] ffffffff Dummy pad word
00000030: [5] aa995566 Sync word
00000034: [6] 20000000 type1 nop 00 wcnt=0
00000038: [6] 3003e001 type1 write 1F wcnt=1 BSPI (BPI/SPI Configuration Option Register)
0000003C: [7] 0000000b
00000040: [6] 30008001 type1 write 04 wcnt=1 CMD (Command Register)
00000044: [7] 00000012 BSPI_READ (BPI/SPI re-initiate bitstream read)
00000048: [6] 20000000 type1 nop 00 wcnt=0
0000004C: [6] 30022001 type1 write 11 wcnt=1 TIMER (Watchdog Timer Register)
00000050: [7] 7fffffff
00000054: [6] 30020001 type1 write 10 wcnt=1 WBSTAR (Warm Boot Start Address Register)
00000058: [7] 00140000
0000005C: [6] 30008001 type1 write 04 wcnt=1 CMD (Command Register)
00000060: [7] 0000000f IPROG (reboot_rst)
00000064: [6] 20000000 type1 nop 00 wcnt=0
00000068: [6] 30008001 type1 write 04 wcnt=1 CMD (Command Register)
0000006C: [7] 00000007 RCRC (Reset CRC register)
00000070: [6] 20000000 type1 nop 00 wcnt=0
00000074: [6] 20000000 type1 nop 00 wcnt=0
00000078: [6] 30026001 type1 write 13 wcnt=1 CRC (CRC Register)
0000007C: [7] 00000000
00000080: [6] 30012001 type1 write 09 wcnt=1 COR0 (Configuration Option Register 0)
00000084: [7] 02003fe5
00000088: [6] 3001c001 type1 write 0E wcnt=1 COR1 (Configuration Option Register 1)
0000008C: [7] 00000000
00000090: [6] 30018001 type1 write 0C wcnt=1 IDCODE (Device ID Register)
00000094: [7] 037c2093
00000098: [6] 30008001 type1 write 04 wcnt=1 CMD (Command Register)
0000009C: [7] 00000009 SWITCH (Switches the CCLK frequency)
000000A0: [6] 20000000 type1 nop 00 wcnt=0
000000A4: [6] 3000c001 type1 write 06 wcnt=1 MASK (Masking Register for CTL0 and CTL1)
000000A8: [7] 00000001
000000AC: [6] 3000a001 type1 write 05 wcnt=1 CTL0 (Control Register 0)
000000B0: [7] 00000101
000000B4: [6] 3000c001 type1 write 06 wcnt=1 MASK (Masking Register for CTL0 and CTL1)
000000B8: [7] 00001000
000000BC: [6] 30030001 type1 write 18 wcnt=1 CTL1 (Control Register 1)
000000C0: [7] 00001000
000000C4: [6] 20000000 type1 nop 00 wcnt=0
000000C8: [6] 20000000 type1 nop 00 wcnt=0
000000CC: [6] 20000000 type1 nop 00 wcnt=0
000000D0: [6] 20000000 type1 nop 00 wcnt=0
000000D4: [6] 20000000 type1 nop 00 wcnt=0
000000D8: [6] 20000000 type1 nop 00 wcnt=0
000000DC: [6] 20000000 type1 nop 00 wcnt=0
000000E0: [6] 20000000 type1 nop 00 wcnt=0
000000E4: [6] 30002001 type1 write 01 wcnt=1 FAR (Frame Address Register)
000000E8: [7] 00000000
000000EC: [6] 30008001 type1 write 04 wcnt=1 CMD (Command Register)
000000F0: [7] 00000001 WCFG (Write Configuration Data
000000F4: [6] 20000000 type1 nop 00 wcnt=0
000000F8: [6] 300046b5 type1 write 02 wcnt=1717 FDRI (Frame Data Register, Input)
000000FC: [7] 00000000

After trying to boot, the BOOT_STATUS register contain all zeros.
The CONFIG_STATUS register has ones in BIT02_PLL_LOCK_STATUS, BIT03_DCI_MATCH_STATUS, BIT08_MODE_PIN_M[0], BIT11_INIT_B_INTERNAL_SIGNAL_STATUS, BIT12_INIT_B_PIN, BIT28_PUDC_B_PIN, and zeros in the rest.
TIMER register and WBSTAR registers has the same contents as the bin file.

What could be wrong? Isn't it suppose to time-out when trying to boot from an empty flash area, and try to reboot from the golden image at address 0?


Also, in some posts on this forums, some people set the following property in the Artix golden xdc:s:
BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT
I haven't found any documentation on this property in any Artix documentation. It seems to be an Ultrascale thing, or am I wrong?
Do I need it? Is there any proper documentation for it?

 

Thanks in advance
Per

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Highlighted
Moderator
Moderator
708 Views
Registered: ‎06-05-2013
Hi per,
Can you add a timer barrier method to make the system more robust. This has been explained in XAPP1247 #page15
BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT: Its by default enable so no need to add this specifically.

Thanks
Harshit
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Highlighted
Moderator
Moderator
709 Views
Registered: ‎06-05-2013
Hi per,
Can you add a timer barrier method to make the system more robust. This has been explained in XAPP1247 #page15
BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT: Its by default enable so no need to add this specifically.

Thanks
Harshit
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Highlighted
Visitor
Visitor
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Registered: ‎10-12-2016

I did it XAPP1081-style instead. That worked for me.
Thanks!