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nekster
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Registered: ‎12-03-2018

Artix-7, using LVDS-2.5

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Hello, i deal first time with xilinx product and i'd like to ask about using LVDS-2.5 in Artix-7. As i understand, i have to supply needed bank 2.5v, but are there any requirements to clock signal, shoud it be differential too? Or i can just use single-ended signal, for example, 100 MHz? Does lvds-2.5 depend on it?

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joancab
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Registered: ‎05-11-2015

LVDS is differential by definition (Low Voltage Differential Signaling). If single ended, is not LVDS. If a cat, not a bird. If a bird, not a cat.

LVDS-capable pins go in pairs, specified in the pinout. All pairs have both pins in the same bank. You are free to double check it.

LVDS doesn't specify frequency. It's up to you. There is probably a minimum (actually for low frequencies like < 50 M, you can just use single ended) and the maximum is set by the FPGA capabilities.

Now about clocks, typically you use the external clock for your FPGA, 20 or 33.333 MHz, whatever. Typically single ended (low frequency). Then with an MMCM you generate the frequency you need, like 100, 200, etc. MHz. If you need to provide or receive a clock, it's also typically LVDS (differential).

Differential signaling is normally associated with high frequencies (> 100 MHz) to be less immune to noise as well as radiate less.

And... I feel this will be next... inside the FPGA all signals are single. There are IBUF and OBUF primitives that interface to differential pin pairs.

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miker
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Registered: ‎11-30-2007

@nekster 

You can reference the 7 Series FPGAs SelectIO Resources User Guide (UG471; v1.10; pp 98-100) for all the details.

  • If you want to drive LVDS (IOSTANDARD = LVDS_25) signal out of an Artix-7 HR IO Bank, then the VCCO must equal 2.5V.
  • If you want to receive an LVDS signal into an Artix-7 HR IO Bank AND utilize the internal differential termination (DIFF_TERM=TRUE), then VCCO must equal 2.5V.
  • If you want to receive an LVDS signal into an Artix-7 HR IO Bank AND utilize an external differential termination resistor, then VCCO can be a voltage that complies with Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard summarized in Note 1.

forums_ug471_table1-55.png

I'm not sure I fully understand your question about clocks.  If you are utilizing an Low Voltage Differential Signaling (LVDS) clock, it must be differential as the IO Standard name implies.  If you want to utilize a clock in an IO Bank where VCCO=2.5V, you can use a single-ended clock using an IO Standard like LVCMOS25, for example.

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nekster
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Registered: ‎12-03-2018

Thank you for answer. 

I think, I'm not enough correct asking the question. How much frequency i should get from oscillator to utilize LVDS-2.5? And should it be connected to the same bank?

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bruce_karaffa
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Registered: ‎06-21-2017

Can you post a block diagram showing what you want to do?  It is hard to understand your question.  Are you using LVDS to bring data into your FPGA or to output data from your FPGA?  Does input data come with its own clock?  Do you need to supply a clock with output data?

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joancab
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Registered: ‎05-11-2015

LVDS is differential by definition (Low Voltage Differential Signaling). If single ended, is not LVDS. If a cat, not a bird. If a bird, not a cat.

LVDS-capable pins go in pairs, specified in the pinout. All pairs have both pins in the same bank. You are free to double check it.

LVDS doesn't specify frequency. It's up to you. There is probably a minimum (actually for low frequencies like < 50 M, you can just use single ended) and the maximum is set by the FPGA capabilities.

Now about clocks, typically you use the external clock for your FPGA, 20 or 33.333 MHz, whatever. Typically single ended (low frequency). Then with an MMCM you generate the frequency you need, like 100, 200, etc. MHz. If you need to provide or receive a clock, it's also typically LVDS (differential).

Differential signaling is normally associated with high frequencies (> 100 MHz) to be less immune to noise as well as radiate less.

And... I feel this will be next... inside the FPGA all signals are single. There are IBUF and OBUF primitives that interface to differential pin pairs.

View solution in original post