cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
517 Views
Registered: ‎11-12-2019

Artix7 LVDS input

Jump to solution

Hi,

  I am new to the FPGA world. I struggled to achieve things up to now myself. I discovered the benefit of this community now. Thank you a lot in advance. I try to interface the LTC6754 LVDS output comparator to my Artix7 Nexys-a7-100t FPGA. I look at the example xdc file and see that all input and outputs are LVCMOS3.3. I shared the datasheet and pictures of lvds input and output. Is it possible to connect the output of the LTC6754 to my FPGA directly.? How can I do it?

Thanks a lot.

Have a nice study.

Regards.

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
351 Views
Registered: ‎01-22-2015

Re: Artix7 LVDS input

Jump to solution

azadozankorkan@anadolu.edu.tr 

If you used the set_property constraints that I showed, then the top-level VHDL component in your project would look something like the following (which I have called TOP.vhd).  The signal called single_end is what you would use elsewhere in your VHDL code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;

entity TOP is
   port(
      LVDS1_P  : in std_logic; 
LVDS1_N : in std_logic
); end TOP;

architecture Behavior of TOP is
signal single_end : std_logic;

begin

IBDS1: IBUFDS
generic map(
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map(
O => single_end,
I => LVDS1_P,
IB => LVDS1_N
);

end Behavior;

The IBUFDS_DIFF_OUT component has a differential signal output and is for advanced users only.  In general, all signals inside the FPGA are single-end (and not differential).

Mark

View solution in original post

8 Replies
Highlighted
489 Views
Registered: ‎01-22-2015

Re: Artix7 LVDS input

Jump to solution

azadozankorkan@anadolu.edu.tr 

Welcome to the Forum!

You may be able to use LVDS_25 to bring the output of LTC6754 into the Artix-7.

Here are things you should do to verify that this is possible.

  • Look at Table 11 in the datasheet, DS181(v1.25), for the Artix-7.  There you will find the specifications for VIDIFF and VICM of LVDS_25.
  • Look in the LTC6754 datasheet.  There you will find specifications for VOD(aka VODIFF) and VOCM for the LVDS output.
  • If LTC6754 VOD meets Artix-7 VIDIFF specification -and- LTC6754 VOCM meets the Artix-7 VICM specification, then you can use LVDS_25 to bring the output of LTC6754 into the Artix-7.

In addition, please read pages 91-93 in UG471(v1.10) and read pages at the following link, which give other import details (eg. an external 100-ohm termination across the LVDS lines is needed).
https://www.xilinx.com/support/answers/43989.html

Cheers,
Mark

Highlighted
438 Views
Registered: ‎11-12-2019

Re: Artix7 LVDS input

Jump to solution

          Thank you a lot. It was very important for me to know LTC6754 can work with artix7 FPGA directly. I understand the logic with your shared files. Sorry for the simple questions but the coming signal form LTC6754 will be 10ns high duration and 1 millisecond period. When lvds signal from 10ns pulse came, I want to see logic 1. Which pins can I connect the lvds output cables to FPGA. I mean I connect one cable to FPGA to make logic 1 signal in FPGA up to now. How can I declare the lvds_25 in xdc file to connect two input to FPGA and FPGA knows this is one differential input and make the std_logic signal one. All IO standards lvcmos33. If one will be lvds_25, should all IO lvds_25? 

Thanks in advance.

Regards.

xdc.JPG
0 Kudos
Highlighted
430 Views
Registered: ‎06-21-2017

Re: Artix7 LVDS input

Jump to solution

Signals that are LVDS should use the LVDS25 IO Standard when connected to an Artix.  Single ended signals should remain LVCMOS.  Is the bank that you are connecting the LVDS to powered by 3.3V as indicated by your xdc file?  If so, this paragraph from the Select IO User's Guide indicates that you cannot use the internal termination resistors of the FPGA and must provide external terminations (100 Ohms across the differential pair) on your board. 

The LVDS_25 I/O standard is only available in the HR I/O banks. It requires a VCCO to be
powered at 2.5V for outputs and for inputs when the optional internal differential
termination is implemented (DIFF_TERM = TRUE).

One more thing.  Take care to connect a differential LVDS pair to a _p, _n pair of pins on the FPGA.

0 Kudos
Highlighted
421 Views
Registered: ‎11-12-2019

Re: Artix7 LVDS input

Jump to solution

Thanks,

I will use an external 100-ohm resistor. I will use lvds as input. Differential pairs are only available for xadc signals which are for analog to digital converter. Should I connect the lvds inputs to jxadc in the photo I shared or can I create differential pair with other single-ended io pins? When I declare lvds_25 in xdc , is it enough or should ı do additional things to make the io standard lvds_25.

Regards.

52f55354-a56c-4aee-a4f4-b3acf39e601f.jpg
0 Kudos
Highlighted
408 Views
Registered: ‎01-22-2015

Re: Artix7 LVDS input

Jump to solution

azadozankorkan@anadolu.edu.tr 

Your Nexys board has the XC7A100T-1CSG324C (Artix-7) FPGA.  As shown in the <package file> for your FPGA, every pin of the FPGA has a pin name.  Table 1-12 of UG475 shows you how to interpret the pin name

You will find that IO pins are usually arranged as differential pairs.  For example, pins H16 and G16 have the pin names IO_L13P_T2_MRCC_15 and IO_L13N_T2_MRCC_15.  As described in Table 1-12 of UG475, the “L13P” and "L13N” indicate that H16 and G16 are a differential pair.  Your LVDS_25 inputs must be connected to a differential pair of pins.

Continuing with the example of using H16 and G16 for LVDS_25,  you would place the following constraints in the Vivado .xdc file.  

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVDS_25 }  [get ports LVDS1_P]
set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVDS_25 }  [get ports LVDS1_N]

Finally, in your HDL code, you will need to instantiate a component called IBUFDS.  Page 355 of UG953 shows you how to instantiate IBUFDS.  The IBUFDS component will convert the LVDS_25 differential-signal into a single-end signal that you can use in your HDL.

Mark

Highlighted
385 Views
Registered: ‎11-12-2019

Re: Artix7 LVDS input

Jump to solution

  Mark thanks a lot. Your explanation is very clear and informative. I learned very good things. I will ask the last question. Page 355 of UG953 shows two inputs and two outputs, should I use the 1 output to get a single-end signal as you said?. I shared the 1 output example of your advised documentation.  As far as I understand, the inputs of the buffer will be inputs of my main ports and I should write lvds_25 to the iostandard section of instantiation. Am I right?

1.JPG
2.JPG
0 Kudos
Highlighted
352 Views
Registered: ‎01-22-2015

Re: Artix7 LVDS input

Jump to solution

azadozankorkan@anadolu.edu.tr 

If you used the set_property constraints that I showed, then the top-level VHDL component in your project would look something like the following (which I have called TOP.vhd).  The signal called single_end is what you would use elsewhere in your VHDL code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;

entity TOP is
   port(
      LVDS1_P  : in std_logic; 
LVDS1_N : in std_logic
); end TOP;

architecture Behavior of TOP is
signal single_end : std_logic;

begin

IBDS1: IBUFDS
generic map(
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map(
O => single_end,
I => LVDS1_P,
IB => LVDS1_N
);

end Behavior;

The IBUFDS_DIFF_OUT component has a differential signal output and is for advanced users only.  In general, all signals inside the FPGA are single-end (and not differential).

Mark

View solution in original post

Highlighted
299 Views
Registered: ‎11-12-2019

Re: Artix7 LVDS input

Jump to solution

      Thank you very much for your guidance and help. You explained in a clear and detailed way. It makes me happy to see people like you who help other people like this. I got how to interface and use lvds_25 signals with Artix7.

Have a nice study.

Regards.

0 Kudos