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502 Views
Registered: ‎12-15-2018

Bit file download mistake

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Hello everyone,

can anybody tell me, if FPGA can be damaged, if I did mistake and download to XC7A35T in package CPG236C (Basys 3) bit file created for XC7A35T in package CSG324I (Digilent Arty) by Vivado Lab? Pins provides output in design for CSG324I are not on CPG236C present. I only download simple design (4 switches input directly to 4 led output, without any process, simply with <= operator on std_logic_vector). How I can test XC7A35T for correct work (eg. interconnection matrix, etc.)? On board demo works well and downloading correct bitstream also.

Thanks in advance for any answer

Best regards

Josef

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1 Solution

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Xilinx Employee
Xilinx Employee
469 Views
Registered: ‎06-06-2018

Re: Bit file download mistake

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Hi @josef_kiefmann,

Even though IDCODE check happens, it will not have information regarding package. so it is not recommended to configure the FPGA with incorrect bitstream. As it will damage the FPGA. please dont even try also.

 

Regards,

Deepak D N

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Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎06-06-2018

Re: Bit file download mistake

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Hi @josef_kiefmann,

Even though IDCODE check happens, it will not have information regarding package. so it is not recommended to configure the FPGA with incorrect bitstream. As it will damage the FPGA. please dont even try also.

 

Regards,

Deepak D N

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463 Views
Registered: ‎12-15-2018

Re: Bit file download mistake

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Hello @ddn,

thank you for your answer. Yes, I will not try this anymore, but if this case have accidentally occurred, is there any potentially case that some large design may not work in future due to some internal broken connection (eg. burned transistor or buffer)? I tested built-in demo (works), I can test inputs and outputs of all pins (where on the board can have access), but I think that these demos doesn't tests all interconnections and blocks. I got an idea, when I download some bitstream (for correct package) and I will have also mask file and I will verify this bitstream and mask with design in FPGA, can I detect problems with physical connection or is it only verifying config SRAM memory? Or is there any other better way to check FPGA for fully functional. For information bad design bitstream was in FPGA about 5 seconds and only uses 4 inputs and 4 outputs, so I think that FPGA might not be crashed.

For addition, I know that this thread is not about Spartan 3E-100 (Basys 2), but I met on it with part similar problem in school 3 years ago. I have downloaded design (some binary or gray counter I think) and after I downloaded design and run it, some segments on display lights although these pins I hadn't used for design (design fully worked but also used pins not described in UCF I think), is it possible this due to selecting unused pins to float and some large design can use these IO as some auxiliary elements?

Best regards

Josef

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462 Views
Registered: ‎12-15-2018

Re: Bit file download mistake

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For addition on Basys 2, in that case I downloaded the bitstream made for the correct package.
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421 Views
Registered: ‎12-15-2018

Re: Bit file download mistake

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I got next idea to check health of my FPGA. If I uderstand, the bitstream in my case contained some routing configuration (so if I only had connection (A8 => H5; C11 => J5; C10 => T9; A10 => T10) between IOBs, am I right? So I can found what pads are on same IOBs on different package and can analyse (eg. with test design), if any damage could occurr, am I right? I found that connections mentioned up was on different package (A17 => unbonded; C16 => unbonded; B16 => V13; C17 => V14) and V13 and V14 when I downloaded this bitstream lights but B16 and C17 was floating, but I think that unconnected input could induce something. And I can now design some test with inputs to outputs (in unbonded case to nearest IOBs) and test functionality. So can this be the correct method to test for broken elements in interconnection? Or I can cool down because bitstream for XC7A35T in any package couldn't switched in interconnection two outputs on same wire and there is only potentially trouble with pads (eg. strong pull down if outside is hard VCC)?

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