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joe306
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Registered: ‎12-07-2018

Boot Memory for Artix 7

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Hello, I am working a design using the Artix 7 part#XC7A35T-1CPG236I. I have not used this FPGA before so my question may be silly. Does this FPGA have its boot memory on chip or do I need an external flash memory? I was reading DS180 page 13 and I believe that an external memory is required. In that case which pins must I connect the flash memory to and how do I configure that in Vivado?

Thank you

Joe

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joancab
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Registered: ‎05-11-2015

zynq ultrascale+ but I don't think it makes much difference, all I needed was an MMCM and a bunch of logic.

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watari
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Hi @joe306 

 

I just ask you before reply.

 

- Does your PCB have an external cpu device ? Ex. Cortex-M1 device. If yes, you might not need an external flash.

- Does your design have Microblaze ? If yes, you have to use an external memory and prepare SREC boot code for boot up Microblaze.

 

My questions are related with my answer.

 

Best regards,

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joe306
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Hello and thank you for responding to my post. I am design a very small board that will interface with a camera using CameraLink and also interfacing with a Frame Grabber over CameraLink. CameraLink is differential pairs so I will have some RS422 devices and the Artix FPGA. I do no know if I will use a MicroBlaze processor. I guess I should assume I will.

Hope this helps.

Thank you

Joe

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joe306
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Hello, I was looking at the Digilent Board ARTY 500-319 board and they connect two SPI FLASH devices pn N25Q128A13EF840E connected to the Configuration pins:

Arty_Config.jpg

I can use this board as a reference. I do need to look into the PROGRAM_B pin, they use a push button which I guess does a warm reset.

Anyways, I'm still researching this topic on boot memory.

Thank you

Joe

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joe306
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I see the flash they are using is obsolete so I need to find an alternative.

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joancab
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I've recently done some cameralink stuff and didn't need any RS422 converters, I just used differential pairs with LVDS, even for the UART comms to the camera. You need to look for these converters able to respond at CL speeds (40 or 80 MHz), plus not adding too much skew or you won't be able to realign signals. Also, because delay of these converters may vary with time, temperature and stock prices, it could be a little piece of Hell on your hands. I may be wrong, but I would need a strong reason to add discrete external components to high speed lines.

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joancab
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There is a number of boot modes, typically the Master SPI is used and you need and external (SPI/ QSPI) flash. The boot modes that don't require external flash involve a microcontroller feeding data to the FPGA (not sure if I can say 'always'). 

Some FPGA are flash-based themselves (most are RAM based) and they don't boot they just start. I think some old Spartan-3 are that technology. So, with RAM based ones, configuration resides outside, either brought by some chip or just laying on a memory.

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joe306
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Hello, I thought I could convert the Diff pairs to single-ended and use less pins on the FPGA. I could go into the FPGA with the Diff pairs but that takes more pins. Also, I should have NOT said RS422 but LVDS modules. I was planning on using the SN65LVDT32B (RX) and SN65LVDS31D (TX) devices. These are faster devices that support 400Mbps data rates. Sometimes it is good to use external components provides a little more protection to the FPGA if someone does something stupid with the cabling.

How does this sound to you?

Thank you

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joe306
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I found an alternative SPI flash memory: MT25QL128ABA1EW9-0SIT TR . I'm trying to find a link on the Xilinx page that lists compatible memory.

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joe306
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This one here MT25QL128ABA8ESF-0AAT TR is a 16-SOIC.

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joe306
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I will be using Vitis 2020 tools. I mention that because in my search for a list of compatible Flash devices I see many references to ISE and IMPACT. Don't know what IMPACT is but I'm not using the ISE tools.

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joancab
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convert the Diff pairs to single-ended and use less pins on the FPGA

Yes, that's one valid reason.

NOT said RS422 but LVDS modules

That's another thing. If the delay variation is small (low skew), should be okay.

external components provides a little more protection to the FPGA

That's indeed another good reason.

someone does something stupid with the cabling

And we all do that sometimes.

It looks sensible. I would just double check how much skew these parts may introduce. Or maybe I'm overdoing things.

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joe306
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Hello, thank you for commenting. Where can I find a list of supported configuration memories for the Artix family? Is there a Technical Reference Manual for the Artix family? I want do know what should be done with the VP/N pins and the VREFP/N pins? Last, does the power rails need to be sequenced?

Thank you very much,

Joe

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joe306
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Hello, quick question for you about the CameraLink project, what FPGA did you use?

Thank you

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joancab
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zynq ultrascale+ but I don't think it makes much difference, all I needed was an MMCM and a bunch of logic.

View solution in original post

joe306
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Thank you, do know the web site that lists the compatible or supported FLASH memory for Artix FPGA's?

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joancab
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XAPP586, that may be of interest to you, has this link:

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest_ise;d=isehelp_start.htm;a=pim_c_introduction_indirect_programming.htm

That is broken even if the doc is from 2020... links are going to become useless... anyways...

UG908 (v2019.2) p. 329 has a 3+ page long list of flash memories.

I would say that any memory would work, it's just Xilinx haven't tested it, in most cases, you know, economical friendship, etc.

joe306
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Thank you very much

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