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Adventurer
Adventurer
402 Views
Registered: ‎09-21-2019

Boot time for spartan 3E

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Hey All,

How to calculate the boot time for spartan 3E?

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Xilinx Employee
Xilinx Employee
384 Views
Registered: ‎06-06-2018

Hi @richa1989 ,

It depends on the bitstream size (a 3S500E is ~2.3Mb), the configuration method, configuration clock rate, and other details.

 

 

From http://www.xilinx.com/support/documentation/application_notes/xapp457.pdf (Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications)
/*
Configuration bitstream loading. The duration of this event, named TBITLOAD for
convenience, is a function of device family, density, configuration clock frequency, and
configuration data port width. Consult the relevant device data sheet for more information.
In general:
TBITLOAD = (Bitstream Length in bits) / ((Clock Frequency in Hz) * (Configuration Port Width in bits))
When using a configuration clock derived from a crystal oscillator, the nominal clock
frequency can be used in the calculation. When the configuration clock is derived from a
ring oscillator or other highly variable source (for example, the Spartan-3 Generation FPGA
is using a “master” configuration mode), use the guaranteed minimum clock frequency in
the calculation.
*/
[There are also useful details in this app note, such as power supply ramp rate, oscillator startup, power on reset, etc.]

 

 

from ds312:
/*
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option.

 

....

ConfigRate CCLK,
Configuration
1, 3, 6,
12, 25, 50
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. 
*/
There is an entire table dedicated to Configuration Clock (CCLK) Characteristics, which can be programmed during bitgen - each setting's min & max values encompass a fairly wide range due to process and other variations.

 

Hopefully this is enough to point you in the right direction.

 

Here's another useful reference: UG331  (Spartan-3E Generation Configuration User Guide)
Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
385 Views
Registered: ‎06-06-2018

Hi @richa1989 ,

It depends on the bitstream size (a 3S500E is ~2.3Mb), the configuration method, configuration clock rate, and other details.

 

 

From http://www.xilinx.com/support/documentation/application_notes/xapp457.pdf (Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications)
/*
Configuration bitstream loading. The duration of this event, named TBITLOAD for
convenience, is a function of device family, density, configuration clock frequency, and
configuration data port width. Consult the relevant device data sheet for more information.
In general:
TBITLOAD = (Bitstream Length in bits) / ((Clock Frequency in Hz) * (Configuration Port Width in bits))
When using a configuration clock derived from a crystal oscillator, the nominal clock
frequency can be used in the calculation. When the configuration clock is derived from a
ring oscillator or other highly variable source (for example, the Spartan-3 Generation FPGA
is using a “master” configuration mode), use the guaranteed minimum clock frequency in
the calculation.
*/
[There are also useful details in this app note, such as power supply ramp rate, oscillator startup, power on reset, etc.]

 

 

from ds312:
/*
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option.

 

....

ConfigRate CCLK,
Configuration
1, 3, 6,
12, 25, 50
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. 
*/
There is an entire table dedicated to Configuration Clock (CCLK) Characteristics, which can be programmed during bitgen - each setting's min & max values encompass a fairly wide range due to process and other variations.

 

Hopefully this is enough to point you in the right direction.

 

Here's another useful reference: UG331  (Spartan-3E Generation Configuration User Guide)
Regards,
Deepak D N
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---------------------------------------------------------------------------

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Adventurer
Adventurer
350 Views
Registered: ‎09-21-2019

Thanks for reply.

I have ported my application from spartan 3E to zynq 7000 board.so this one making the boot time diffrences.how could i optimize the boot time so that it can become equals to spartan 3E boot time?

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Adventurer
Adventurer
347 Views
Registered: ‎09-21-2019

My bit file size is 375200 bits and clock 50MHz.configuration port width is x1

so according to these parametrs boot time should be 75 ms.Am i right?

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Xilinx Employee
Xilinx Employee
323 Views
Registered: ‎06-06-2018

Hi @richa1989 ,

For Zynq 7000 family devices, please refer this AR#55572 to calculate boot time.

The above AR particularly highlights settings and considerations to achieve better timing and bandwidth results during different boot stages.

Hope this helps.

If you need more help for Zynq devices. Please post your further queries in Embedded blog, so that you will get better help. This blog is related to non Zynq devices. Thanks for understanding.

 

Regards,
Deepak D N
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